STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS

Microelectronic devices and systems have been extensively utilized in a variety of radiation environments, ranging from the low-earth orbit to the ground level. A high-energy particle from such an environment may cause voltage/current transients, thereby inducing Single Event Effect (SEE) errors in an Integrated Circuit (IC). Ever since the first SEE error was reported in 1975, this community has made tremendous progress in investigating the mechanisms of SEE and exploring radiation tolerant techniques. However, as the IC technology advances, the existing hardening techniques have been rendered less effective because of the reduced spacing and charge sharing between devices. The Semiconductor Industry Association (SIA) roadmap has identified radiation-induced soft errors as the major threat to the reliable operation of electronic systems in the future. In digital systems, hardening techniques of their core components, such as latches, logic, and clock network, need to be addressed. Two single event tolerant latch designs taking advantage of feedback transistors are presented and evaluated in both single event resilience and overhead. These feedback transistors are turned OFF in the hold mode, thereby yielding a very large resistance. This, in turn, results in a larger feedback delay and higher single event tolerance. On the other hand, these extra transistors are turned ON when the cell is in the write mode. As a result, no significant write delay is introduced. Both designs demonstrate higher upset threshold and lower cross-section when compared to the reference cells. Dynamic logic circuits have intrinsic single event issues in each stage of the operations. The worst case occurs when the output is evaluated logic high, where the pull-up networks are turned OFF. In this case, the circuit fails to recover the output by pulling the output up to the supply rail. A capacitor added to the feedback path increases the node capacitance of the output and the feedback delay, thereby increasing the single event critical charge. Another differential structure that has two differential inputs and outputs eliminates single event upset issues at the expense of an increased number of transistors. Clock networks in advanced technology nodes may cause significant errors in an IC as the devices are more sensitive to single event strikes. Clock mesh is a widely used clocking scheme in a digital system. It was fabricated in a 28nm technology and evaluated through the use of heavy ions and laser irradiation experiments. Superior resistance to radiation strikes was demonstrated during these tests. In addition to mitigating single event issues by using hardened designs, built-in current sensors can be used to detect single event induced currents in the n-well and, if implemented, subsequently execute fault correction actions. These sensors were simulated and fabricated in a 28nm CMOS process. Simulation, as well as, experimental results, substantiates the validity of this sensor design. This manifests itself as an alternative to existing hardening techniques. In conclusion, this work investigates single event effects in digital systems, especially those in deep-submicron or advanced technology nodes. New hardened latch, dynamic logic, clock, and current sensor designs have been presented and evaluated. Through the use of these designs, the single event tolerance of a digital system can be achieved at the expense of varying overhead in terms of area, power, and delay

Digitale Schaltungstechniken für Sub-100 nm-CMOS-Technologien

Auch in Zukunft wird sich der Trend hin zu größeren Integrationsdichten, höherer Schaltgeschwindigkeit und geringerer Leistungsaufnahme fortsetzen, wenn es gelingt, durch geeignete schaltungstechnische Maßnahmen die Schaltgeschwindigkeit zu erhöhen und höhere Transistor-Leckströme in der Gesamtschaltung zu unterdrücken. In der vorliegenden Arbeit wird der Trade-off zwischen Leckstrom und Schaltgeschwindigkeit übergreifend vom Einzeltransistor, über elementare Logikgatter und Ringoszillatoren bis hin zu einem 32-bit-Addierer hardwarebasiert untersucht. Es werden dazu die physikalischen Grundlagen von Leckströmen und Schaltgeschwindigkeiten aufgezeigt sowie neue Schaltungstechniken vorgestellt, die Transistoren unterschiedlicher Oxiddicke und Schwellenspannung in einer Schaltung zu kombinieren. Es wurde ein Sense-Amplifier-Flip-Flop entwickelt, das bei kleinerer Verzögerungszeit eine geringere aktive Leistungsaufnahme aufweist. Die vorgestellten Techniken werden in einer 90nm-CMOS-Technologie anhand eines 32-bit-Parallel-Addierers erprobt

NASA Thesaurus. Volume 1: Hierarchical listing

There are 16,713 postable terms and 3,716 nonpostable terms approved for use in the NASA scientific and technical information system in the Hierarchical Listing of the NASA Thesaurus. The generic structure is presented for many terms. The broader term and narrower term relationships are shown in an indented fashion that illustrates the generic structure better than the more widely used BT and NT listings. Related terms are generously applied, thus enhancing the usefulness of the Hierarchical Listing. Greater access to the Hierarchical Listing may be achieved with the collateral use of Volume 2 - Access Vocabulary

NASA thesaurus. Volume 1: Hierarchical Listing

There are over 17,000 postable terms and nearly 4,000 nonpostable terms approved for use in the NASA scientific and technical information system in the Hierarchical Listing of the NASA Thesaurus. The generic structure is presented for many terms. The broader term and narrower term relationships are shown in an indented fashion that illustrates the generic structure better than the more widely used BT and NT listings. Related terms are generously applied, thus enhancing the usefulness of the Hierarchical Listing. Greater access to the Hierarchical Listing may be achieved with the collateral use of Volume 2 - Access Vocabulary and Volume 3 - Definitions

NASA thesaurus. Volume 2: Access vocabulary

The Access Vocabulary, which is essentially a permuted index, provides access to any word or number in authorized postable and nonpostable terms. Additional entries include postable and nonpostable terms, other word entries, and pseudo-multiword terms that are permutations of words that contain words within words. The Access Vocabulary contains 40,738 entries that give increased access to the hierarchies in Volume 1 - Hierarchical Listing

NASA thesaurus. Volume 2: Access vocabulary

The access vocabulary, which is essentially a permuted index, provides access to any word or number in authorized postable and nonpostable terms. Additional entries include postable and nonpostable terms, other word entries and pseudo-multiword terms that are permutations of words that contain words within words. The access vocabulary contains almost 42,000 entries that give increased access to the hierarchies in Volume 1 - Hierarchical Listing

Charge-sharing alleviation and detection for CMOS domino circuits

Abstract—Charge sharing, which occurs in any complementary metal-oxide-semiconductor (CMOS) domino gate, may degrade the output voltage level or may even cause an erroneous output value. In this paper, this problem is thoroughly investigated by considering circuit topology and circuit function. We describe a method to measure the sensitivity [called charge-sharing (CS) vulnerability] of the CS problem for each domino gate. A method to derive the CS vulnerability and the test vector for each domino gate is suggested. We also propose a transistor reordering method to dramatically reduce the CS vulnerabilities for all domino gates so that the CS problem can be alleviated. We also prove theoretically that a set of test vectors generated for single charge-sharing faults (SCSFs) can also detect all multiple charge-sharing faults (MCSFs). This good property significantly guarantees the test quality for the CS faults of domino circuits. Index Terms—Charge sharing, CS vulnerability, domino circuit, multiple faults, transistor reordering. I