176 research outputs found
Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio
A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation
Discrete-Time receivers for software-defined radio: challenges and solutions
Abstract—CMOS radio receiver architectures, based on radio frequency (RF) sampling followed by discrete-time (DT) signal processing via switched-capacitor circuits, have recently been proposed for dedicated radio standards. This paper explores the suitability of such DT receivers for highly flexible softwaredefined radio (SDR) receivers. Via symbolic analysis and simulations we analyze the properties of DT receivers, and show that at least three challenges exist to make a DT receiver work for SDR: 1) the sampling clock frequency is related to the radio frequency, complicating baseband filter design; 2) a frequencydependent phase shift is introduced by pseudo-quadrature and pseudo-differential sampling; 3) the conversion gain of a charge sampling front-end is strongly frequency-dependent. Some potential solutions are also suggested for each challenge. Compared to a mixer based radio receiver, extra costs are needed to solve these problems
Joint synchronization and calibration of multi-channel transform-domain charge sampling receivers
Transform-domain (TD) sampling is seen as a potential candidate for wideband
and ultra-wideband high-performance receivers and is investigated in detail in this
research. TD receivers expand the signal over a set of basis functions and operate on
the digitized basis coefficients. This parallel digital signal processing relaxes the sampling requirements opening the doors to higher dynamic range and wider bandwidth
in receivers. This research is focused on the implementation of a high performance
multi-channel wideband receiver that is based on Frequency-domain (FD) sampling,
a special case of TD sampling.
To achieve high dynamic ranges in these receivers, it is critical that the digital
post processing block matches the analog RF front end accurately. This accurate
matching has to be ensured across several process variations, mismatches and o�sets
that can be present in integrated circuit implementations. A unified model has been
defined for the FD multi-channel receiver that contains all these imperfections and
a joint synchronization and calibration technique, based on the Least-mean-squared
(LMS) algorithm, is presented to track them. A maximum likelihood (ML) algorithm
is used to estimate the frequency offset in carriers which is corrected prior to LMS
calibration. Simulation results are provided to support these concepts.
The sampling circuits in FD receivers are based on charge-sampling and a multi-channel charge-sampling receiver creates an inherent sinc filter-bank that has several
advantages compared to the conventional analog filter banks used in other multi-channel receivers. It is shown that the sinc filter banks, besides reduced analog
complexity, have very low computational complexity in data estimation which greatly
reduces the digital power consumption of these filters. The digital complexity of data
estimation in the sinc fiter bank is shown to be less than 1=10th of the complexity
in analog filter banks
Analog baseband circuits for sensor systems
This thesis is composed of six publications and an overview of the research topic, which also summarizes the work. The research presented in this thesis focuses on research into analog baseband circuits for sensor systems. The research is divided into three different topics: the integration of analog baseband circuits into a radio receiver for sensor applications; the integration of an ΔΣ modulator A/D converter into a GSM/WCDMA radio receiver for mobile phones, and the integration of algorithmic A/D converters for a capacitive micro-accelerometer interface. All the circuits are implemented using deep sub-micron CMOS technologies.
The work summarizes the design of different blocks for sensor systems. The research into integrated analog baseband circuits for a radio receiver focuses on a circuit structures with a very low power dissipation and that can be implemented using only standard CMOS technologies.
The research into integrated ΔΣ modulator A/D converter design for a GSM/WCDMA radio receiver for mobile phones focuses on the implications for analog circuit design emerging from using a very deep sub-micron CMOS process.
Finally, in the research into algorithmic A/D converters for a capacitive microaccelerometer interface, new ways of achieving a good performance with low power dissipation, while also minimizing the silicon area of the integrated A/D converter are introduced
Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications
Imperial Users onl
Implementation of a 1GHZ frontend using transform domain charge sampling techniques
The recent popularity and convenience of Wireless communication and the need for integration demands the development of Software Defined Radio (SDR). First defined by Mitoal, the SDR processed the entire bandwidth using a high resolution and high speed ADC and remaining operations were done in DSP. The current trend in SDRs is to design highly reconfigurable analog front ends which can handle narrow-band and wideband standards, one at a time. Charge sampling has been widely used
in these architectures due to the built in antialiasing capabilities, jitter robustness at high signal frequencies and flexibility in filter design. This work proposed a 1GHz wideband front end aimed at SDR applications using Transform Domain (TD) sampling techniques. Frequency Domain (FD) sampling, a special case of TD sampling, efficiently parallelizes the signal for digital processing, relaxing the sampling requirements and enabling parallel digital processing at a much
lower rate and is a potential candidate for SDR. The proposed front end converts the RF signal into current and then it is downconverted using passive mixers. The front end has five parallel paths, each acting on a part of the spectrum effectively parallelizing the front end and relaxing the requirements. An overlap introduced between successive integration windows for jitter robustness was exploited to create
a novel sinc2 downsample by two filter topology. This topology was compared to a conventional topology and found to be equivalent and area efficient by about 44%. The proposed topology was used as a baseband filter for all paths in the front end. The chip was sent for fabrication in 45nm technology. The active area of the chip was 6:6mm2. The testing and measurement of the chip still remains to be done
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