Frequency Domain Hybrid-ARQ Chase Combining for Broadband MIMO CDMA Systems

In this paper, we consider high-speed wireless packet access using code division multiple access (CDMA) and multiple-input multiple-output (MIMO). Current wireless standards, such as high speed packet access (HSPA), have adopted multi-code transmission and hybrid-automatic repeat request (ARQ) as major technologies for delivering high data rates. The key technique in hybrid-ARQ, is that erroneous data packets are kept in the receiver to detect/decode retransmitted ones. This strategy is refereed to as packet combining. In CDMA MIMO-based wireless packet access, multi-code transmission suffers from severe performance degradation due to the loss of code orthogonality caused by both interchip interference (ICI) and co-antenna interference (CAI). This limitation results in large transmission delays when an ARQ mechanism is used in the link layer. In this paper, we investigate efficient minimum mean square error (MMSE) frequency domain equalization (FDE)-based iterative (turbo) packet combining for cyclic prefix (CP)-CDMA MIMO with Chase-type ARQ. We introduce two turbo packet combining schemes: i) In the first scheme, namely "chip-level turbo packet combining", MMSE FDE and packet combining are jointly performed at the chip-level. ii) In the second scheme, namely "symbol-level turbo packet combining", chip-level MMSE FDE and despreading are separately carried out for each transmission, then packet combining is performed at the level of the soft demapper. The computational complexity and memory requirements of both techniques are quite insensitive to the ARQ delay, i.e., maximum number of ARQ rounds. The throughput is evaluated for some representative antenna configurations and load factors to show the gains offered by the proposed techniques.Comment: Submitted to IEEE Transactions on Vehicular Technology (Apr 2009

An algebra and a logic for NC1

Presented here are an algebra and a logic characterizing the complexity class NC1, which consists of functions computed by uniform families of polynomial size, log depth circuits. In both characterizations, NC1 functions are regarded as functions from one class of finite relational structures to another. In the algebraic characterization a recursion scheme called upward tree recursion is applied to a class of simple functions. In the logical characterization, first-order logic is augmented by an operator for defining relations by primitive recursion where it is assumed that every structure has an underlying relation BIT giving the binary representations of integers.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/28501/1/0000298.pd

Picture-Hanging Puzzles

We show how to hang a picture by wrapping rope around n nails, making a polynomial number of twists, such that the picture falls whenever any k out of the n nails get removed, and the picture remains hanging when fewer than k nails get removed. This construction makes for some fun mathematical magic performances. More generally, we characterize the possible Boolean functions characterizing when the picture falls in terms of which nails get removed as all monotone Boolean functions. This construction requires an exponential number of twists in the worst case, but exponential complexity is almost always necessary for general functions.Comment: 18 pages, 8 figures, 11 puzzles. Journal version of FUN 2012 pape

Efficient Implementation of Elliptic Curve Cryptography on FPGAs

This work presents the design strategies of an FPGA-based elliptic curve co-processor. Elliptic curve cryptography is an important topic in cryptography due to its relatively short key length and higher efficiency as compared to other well-known public key crypto-systems like RSA. The most important contributions of this work are: - Analyzing how different representations of finite fields and points on elliptic curves effect the performance of an elliptic curve co-processor and implementing a high performance co-processor. - Proposing a novel dynamic programming approach to find the optimum combination of different recursive polynomial multiplication methods. Here optimum means the method which has the smallest number of bit operations. - Designing a new normal-basis multiplier which is based on polynomial multipliers. The most important part of this multiplier is a circuit of size $O(n \log n)$ for changing the representation between polynomial and normal basis