Yield and Reliability Analysis for Nanoelectronics

As technology has continued to advance and more break-through emerge, semiconductor devices with dimensions in nanometers have entered into all spheres of our lives. Accordingly, high reliability and high yield are very much a central concern to guarantee the advancement and utilization of nanoelectronic products. However, there appear to be some major challenges related to nanoelectronics in regard to the field of reliability: identification of the failure mechanisms, enhancement of the low yields of nano products, and management of the scarcity and secrecy of available data [34]. Therefore, this dissertation investigates four issues related to the yield and reliability of nanoelectronics. Yield and reliability of nanoelectronics are affected by defects generated in the manufacturing processes. An automatic method using model-based clustering has been developed to detect the defect clusters and identify their patterns where the distribution of the clustered defects is modeled by a new mixture distribution of multivariate normal distributions and principal curves. The new mixture model is capable of modeling defect clusters with amorphous, curvilinear, and linear patterns. We evaluate the proposed method using both simulated and experimental data and promising results have been obtained. Yield is one of the most important performance indexes for measuring the success of nano fabrication and manufacturing. Accurate yield estimation and prediction is essential for evaluating productivity and estimating production cost. This research studies advanced yield modeling approaches which consider the spatial variations of defects or defect counts. Results from real wafer map data show that the new yield models provide significant improvement in yield estimation compared to the traditional Poisson model and negative binomial model. The ultra-thin SiO2 is a major factor limiting the scaling of semiconductor devices. High-k gate dielectric materials such as HfO2 will replace SiO2 in future generations of MOS devices. This study investigates the two-step breakdown mechanisms and breakdown sequences of double-layered high-k gate stacks by monitoring the relaxation of the dielectric films. The hazard rate is a widely used metric for measuring the reliability of electronic products. This dissertation studies the hazard rate function of gate dielectrics breakdown. A physically feasible failure time distribution is used to model the time-to-breakdown data and a Bayesian approach is adopted in the statistical analysis

Development and Characterization of Lithium Indium Diselenide for Neutron Detection and Imaging Applications

Lithium indium diselenide [LISe] is under development as a single crystal semiconductor detector for neutron detection applications. Enriched in lithium-6, a neutron sensitive isotope, this wide-band gap semiconductor possesses the inherent neutron-gamma discrimination afforded by the thermal neutron capture reaction energy while providing distinct efficiency advantages over lithiated conversion layer detectors. The overarching theme of this work is to characterize the fundamental properties of this material to optimize its performance in neutron detection applications. The work presented here includes the identification of a suitable metallurgical contact for advanced detector fabrication, fundamental electronic property characterization, and proof-of-principle fast neutron imaging performance. Candidate contact materials were deposited through radio frequency magnetron sputtering. The primary metrics used to identify a robust contact were adhesion to the LISe surface and current voltage characteristics. Among the numerous contacts investigated, indium demonstrated the best adhesion properties. Its viability was demonstrated through the fabrication of a pixelated thermal neutron imaging detector (LTNI). Charge generation, transport, and trapping properties were investigated with emphasis on the stability of these properties post-operation in high thermal neutron flux fields. Neutron and alpha spectroscopy, photoinduced current transient spectroscopy, Raman spectroscopy, trap-filled limited voltage, and photoconductivity measurements were used to probe the charge transport and trapping mechanisms. Moderate transport properties were identified with respect to comparable technologies. Defect studies demonstrated that the type and density of defects strongly influenced performance of the detector. Encouraged by the performance of LTNI, an imaging detector was fabricated by coupling a LISe crystal to a 256 x 256 channel Timepix Application Specific Integrated Circuit to maximize spatial resolution. The fast neutron spatial resolution for 9MeV [electron-Volts] neutrons was investigated via a knife edge experiment. The measured efficiency was in agreement with the Evaluated Nuclear Data File cross-section database. The ultimate spatial resolution of the system was determined as 1.55 millimeters via the 10-90% decrease in contrast of the one-dimensional edge spread function. In conclusion, this material has been shown to exhibit suitable properties warranting further development for high efficiency slow neutron applications guided by the results of this work

Proceedings of the third French-Ukrainian workshop on the instrumentation developments for HEP

The reports collected in these proceedings have been presented in the third French-Ukrainian workshop on the instrumentation developments for high-energy physics held at LAL, Orsay on October 15-16. The workshop was conducted in the scope of the IDEATE International Associated Laboratory (LIA). Joint developments between French and Ukrainian laboratories and universities as well as new proposals have been discussed. The main topics of the papers presented in the Proceedings are developments for accelerator and beam monitoring, detector developments, joint developments for large-scale high-energy and astroparticle physics projects, medical applications.Comment: 3rd French-Ukrainian workshop on the instrumentation developments for High Energy Physics, October 15-16, 2015, LAL, Orsay, France, 94 page

Space radiation equivalence for effects on transistors Final report, 15 May 1965 - 15 Nov. 1966

Space radiation equivalences for permanent damage to silicon transistors by measuring changes in transistor parameters after exposure to proton, electron, and gamma ray irradiatio

Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs

The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies. The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification

Fundamental Sensor Development in Electrical Resistance Tomography

This paper will provide a fundamental understanding of one of the most commonly used tomography, Electrical Resistance Tomography (ERT). Unlike the other tomography systems, ERT displayed conductivity distribution in the Region of Interest (ROI) and commonly associated to Sensitivity Theorem in their image reconstruction. The fundamental construction of ERT includes a sensor array spaced equally around the imaged object periphery, a Data Acquisition (DAQ), image reconstruction and display system. Four ERT data collection strategies that will be discussed are Adjacent Strategy, Opposite Strategy, Diagonal Strategy and Conducting Boundary Strategy. We will also explain briefly on some of the possible Data Acquisition System (DAQ), forward and inverse problems, different arrangements for conducting and non-conducting pipes and factors that influence sensor arrays selections

Photon manipulation in silicon nanophotonic circuits

Quantum-based communication systems can potentially achieve the ultimate security from eavesdropping and greatly reduce the operating powers on chip. Light-speed transmission, noise immunity, and low noise properties make photons indispensable for quantum communication to transfer a quantum state through a transmission line. Furthermore, the field of silicon nanophotonics is fast growing field which is driven by the attractive and promising improvements it has to offer in high speed communication systems and on chip optical interconnects. Consequently, there is a high demand to develop the building blocks for photon manipulation in silicon nanophotonic circuits. The goal of the work is to enable high performance optoelectronic computing and communication systems that overcome the barriers of electronics and dramatically enhance the performance of circuits and systems. We will focus our attention on solving some of the issues with the current systems regarding photon storage, routing, isolation, switching, and energy conversion. We realize a continuously tunable optical memory which breaks the time-bandwidth limit by more than thirty times. This enabled the storage of ultra-short pulses of light for hundreds of picoseconds. Also, we investigate on-chip photon scattering when transmitted through micro-scale optical cavities. In addition, we develop novel dynamic quantum mechanical models that predict quantum-like behavior of single and multi-photon wavepackets. Furthermore, we report for the first time that efficient red shifts in silicon are achievable with free carrier injection which generally produces blue wavelength shifts. We realize adiabatic wavelength conversion and discrete photonic transitions of single photons in silicon cavities. Moreover, we demonstrate a basic quantum network on chip with an on-chip photon source. We present a novel design for CMOS compatible optical isolator on silicon chip using a system of active cavities. And finally, we analyze a novel ultra-fast broadband modulator in silicon based on free-carrier absorption effect in SOI waveguides integrated with Schottky diodes

Physics of the Cosmos (PCOS) Program Technology Development 2018

We present a final report on our program to raise the Technology Readiness Level (TRL) of enhanced chargecoupleddevice (CCD) detectors capable of meeting the requirements of Xray grating spectrometers (XGS) and widefield Xray imaging instruments for small, medium, and large missions. Because they are made of silicon, all Xray CCDs require blocking filters to prevent corruption of the Xray signal by outofband, mainly optical and nearinfrared (nearIR) radiation. Our primary objective is to demonstrate technology that can replace the fragile, extremely thin, freestanding blocking filter that has been standard practice with a much more robust filter deposited directly on the detector surface. Highperformance, backilluminated CCDs have flown with freestanding filters (e.g., one of our detectors on Suzaku), and other relatively lowperformance CCDs with directly deposited filters have flown (e.g., on the Xray Multimirror MissionNewton, XMMNewton Reflection Grating Spectrometer, RGS). At the inception of our program, a highperformance, backilluminated CCD with a directly deposited filter has not been demonstrated. Our effort will be the first to show such a filter can be deposited on an Xray CCD that meets the requirements of a variety of contemplated future instruments. Our principal results are as follows: i) we have demonstrated a process for direct deposition of aluminum optical blocking filters on backilluminated MIT Lincoln Laboratory CCDs. Filters ranging in thickness from 70 nm to 220 nm exhibit expected bulk visibleband and Xray transmission properties except in a small number (affecting 1% of detector area) of isolated detector pixels ("pinholes"), which show higherthanexpected visibleband transmission; ii) these filters produce no measurable degradation in softXray spectral resolution, demonstrating that direct filter deposition is compatible with the MIT Lincoln Laboratory backillumination process; iii) we have shown that under sufficiently intense visible and nearIR illumination, outofband light can enter the detector through its sidewalls and mounting surfaces, compromising detector performance. This 'sidewall leakage' has been observed, for example, by a previous experiment on the International Space Station during its orbitday operations. We have developed effective countermeasures for this sidewall leakage; iv) we developed an exceptionally productive collaboration with the Regolith Xray Imaging Spectrometer (REXIS) team. REXIS is a student instrument now flying on the Origins Spectral Interpretation Resource Identification Security - Regolith Explorer (OSIRISREx) mission. REXIS students participated in our filter development program, adopted our technology for their flight instrument, and raised the TRL of this technology beyond our initial goals. This Strategic Astrophysics Technology (SAT) project, a collaboration between the MKI and MIT Lincoln Laboratory, began July 1, 2012, and ended on June 30, 2018

The Impact of Interface States on Sub-Threshold Leakage and Power Management in CMOS Devices and Circuits

Space applications expose electronic systems to levels of radiation that are damaging to the individual components. Considerable effort has gone into the "hardening" of electronic components against total-dose damage by ionizing radiation. This thesis explores the degree to which commercial-of-the-shelf parts are affected by ionizing radiation. In particular, concentration is on the effect of interface state generation resulting from ionizing radiation on overall device performance. Various sized 0.13μm MOSFET devices were simulated, fabricated, irradiated and tested. Significant increases in the sub-threshold swing and leakage current were observed following a 1MRad total-dose gamma ray irradiation. Subsequently, logic inverter structures exhibited increased sub-threshold swing and total power dissipation following simulations that modeled increasing radiation exposure. Finally, an 11-stage ring oscillator experiment was conducted. A decrease in power for increased irradiations was observed in previous work [49], but without explanation. This work attempts to provide a logical framework for understanding this observation