An investigation of temperature sensitive electrical parameters for SiC power MOSFETs

This paper examines dynamic Temperature Sensitive Electrical Parameters (TSEPs) for SiC MOSFETs. It is shown that the output current switching rate (dIDS/dt) coupled with the gate current plateau (IGP) during turn-ON would be the most effective under specific operating conditions. Both parameters increase with the junction temperature of the device as a result of the negative temperature coefficient of the threshold voltage. The temperature dependency of dIDS/dt has been shown to increase with the device current rating (due to larger input capacitance) and external gate resistance (RGEXT). However, as dIDS/dt is increased by using a small RGEXT, parasitic inductance suppresses the temperature sensitivity of the drain and gate current transients by reducing the “effective gate voltage” on the device. Since the temperature sensitivity of dIDS/dt is at the highest with maximum RGEXT, there is a penalty from higher switching losses when this method is used in real time for junction temperature sensing. This paper investigates and models the temperature dependency of the gate and drain current transients as well as the compromise between the increased switching loss and the potential to implement effective condition monitoring using the evaluated TSEPs

Analytical modeling of switching energy of silicon carbide Schottky diodes as functions of dIDS/dt and temperature

SiC Schottky Barrier diodes (SiC SBD) are known to oscillate/ring in the output terminal when used as free-wheeling diodes in voltage-source converters. This ringing is due to RLC resonance among the diode capacitance, parasitic resistance, and circuit stray inductance. In this paper, a model has been developed for calculating the switching energy of SiC diodes as a function of the switching rate (dIDS/dt of the commutating SiC MOSFET) and temperature. It is shown that the damping of the oscillations increases with decreasing temperature and decreasing dIDS/dt. This in turn determines the switching energy of the diode, which initially decreases with decreasing dIDS/dt and subsequently increases with decreasing dIDS/dt thereby indicating an optimal dIDS/dt for minimum switching energy. The total switching energy of the diode can be subdivided into three phases namely the current switching phase, the voltage switching phase, and the ringing phase. Although the switching energy in the current switching phase decreases with increasing switching rate, the switching energy of the voltage and ringing phase increases with the switching rate. The model developed characterizes the dependence of diode's switching energy on temperature and dIDS/dt, hence, can be used to predict the behavior of the SiC SBD

Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

Measuring Terminal Capacitance and Its Voltage Dependency for High-Voltage Power Devices

The switching behavior of semiconductor devices responds to charge/discharge phenomenon of terminal capacitance in the device. The differential capacitance in a semiconductor device varies with the applied voltage in accordance with the depleted region thickness. This study develops a C - V characterization system for high-voltage power transistors (e.g., MOSFET, insulated gate bipolar transistor, and JFET), which realizes the selective measurement of a specified capacitance from among several capacitances integrated in one device. Three capacitances between terminals are evaluated to specify device characteristics-the capacitance for gate-source, gate-drain, and drain-source. The input, output, and reverse transfer capacitance are also evaluated to assess the switching behavior of the power transistor in the circuit. Thus, this paper discusses the five specifications of a C -V characterization system and its measurement results. Moreover, the developed C -V characterization system enables measurement of the transistor capacitances from its blocking condition to the conducting condition with a varying gate bias voltage. The measured C -V characteristics show intricate changes in the low-bias-voltage region, which reflect the device structure. The monotonic capacitance change in the high-voltage region is attributable to the expansion of the depletion region in the drift region. These results help to understand the dynamic behavior of high-power devices during switching operation

Analysis of the 1st and 3rd Quadrant Transients of Symmetrical and Asymmetrical Double-Trench SiC Power MOSFETs

In this paper, performance at 1 st and 3 rd quadrant operation of Silicon and Silicon Carbide (SiC) symmetrical and asymmetrical double-trench, superjunction and planar power MOSFETs is analysed through a wide range of experimental measurements using compact modeling. The devices are evaluated on a high voltage clamped inductive switching test rig and switched at a range of switching rates at elevated junction temperatures. It is shown, experimentally, that in the 1 st quadrant, CoolSiC (SiC asymmetrical double-trench) MOSFET and SiC symmetrical double-trench MOSFET demonstrate more stable temperature coefficients. Silicon Superjunction MOSFETs exhibits the lowest turn-off switching rates due to the large input capacitance. The evaluated SiC Planar MOSFET also performs sub-optimally at turn-on switching due to its higher input capacitance and shows more temperature sensitivity due to its lower threshold voltage. In the 3 rd quadrant, the relatively larger reverse recovery charge of Silicon Superjunction MOSFET negatively impacts the turn-OFF transients compared with the SiC MOSFETs. It is also seen that among the SiC MOSFETs, the two double-trench MOSFET structures outperform the selected SiC planar MOSFET in terms of reverse recovery

A step-by-step modelling approach for SiC half-bridge modules considering temperature characteristics

In this paper, a detailed step-by-step modellingapproach is proposed for Silicon Carbide (SiC) MOSFET half-bridge power modules. The drain-to-source current, anti-paralleldiode and parasitic capacitors are accurately modelled consider-ing temperature dependency. A step-by-step parameter extractionmethod based on datasheet is introduced. A SPICE model is builtbased on the proposed modelling approach for a commercialpower module. The model is verified by comparing experimentand PSpice simulation results of the same double pulse tester(DPT), which proves the effectiveness of the modelling approachfor analysing switching losses and converter design. The proposedmodelling approach can help the converter designers quickly andaccurately develop their own models for SiC MOSFET powermodules

Analysis of Parasitic Oscillations in Commutation Cells with High Voltage Power MOSFETs

The dynamic behavior of power semiconductor devices with decreasing area-specic on resistances is more and more inf uenced by parasitic characteristics of packages and PCBs. These parasitic characteristics can increase the switching times of power semiconductors andhence reduce the efficiency of power electronic circuits. Furthermore, during commutation the reliability of circuits can be compromised by parasitic oscillations with temporarily increasing amplitudes. Optimized parasitic characteristics of packages and PCBs are thereforenecessary. This applies in particular, if fast power semiconductors are used. Using the example of a one quadrant buck converter topology with a high voltage power MOSFET and a SiC Schottky diode, in this work a methodology is developed that enables the predictionof parasitic oscillations with temporarily increasing amplitudes during commutation and the improvement of the stability of commutation cells. Thereto, suitable circuit models of the power semiconductors and the semiconductor's environment are required. Large-signal models of power MOSFETs and Schottky diodes are deduced for the relevant operating conditions. The combination of curve tracer and short circuit measurements allows the static parameterization of the MOSFET model for the regarded operating range. It is shown that the MOSFET's capacitances can be determined from dynamic measurements. Compared to capacitances measured in accordance with DIN ICE 747, the dynamic capacitances result in an improved conformity of simulations and measurements. The parasitic characteristics of the PCB and packages are modeled with coupling capacitances and effective resistances and inductances. The parameterization of the model is based on quasi-static field simulations of the 3D models of the PCB and packages. The derived behavioral models of the power semiconductors and the electrical interconnections of the PCB and packages are combined with simple models of the DC voltage link, the driver and the load circuit to the model of the buck converter topology. The comparison of measured and simulated switching characteristics approves the proposed buck converter model and the determined parameterization. For the relevant operating points of the buck converter topology, small-signal equivalent circuit models are deduced. It is shown that the stability analysis of the small-signal models enables the prediction of parasitic oscillations with temporarily increasing oscillations during commutation. From the stability analysis of the small-signal models with different parameterizations, measures for an improved stability of the commutation cell are concluded. Design iterations and development costs can be saved with the presented methodology.Das dynamische Verhalten von Leistungshalbleitern mit immer kleineren flächenspezifischen Einschaltwiderständen wird stärker durch die parasitären Eigenschaften von Gehäusen und Leiterplatten beeinflusst. So können die Parasiten die Schaltzeiten der Halbleiter erhöhen und damit die Effizienz von leistungselektronischen Schaltungen verringern. Außerdem kann die Zuverlässigkeit von Schaltungen während der Kommutierung durch parasitäre Schwingungen mit zwischenzeitlich steigenden Amplituden beeinträchtigt werden. Insbesondere bei Verwendung von schnellen Leistungshalbleitern ist deshalb die Optimierung der parasitären Eigenschaften von Gehäusen und Leiterplatten notwendig. Am Beispiel eines Tiefsetzstellers mit einem Hochvolt-Leistungs-MOSFET und einer SiC Schottky-Diode wird in dieser Arbeit eine Methodik entwickelt, die die Vorhersage von parasitären Schwingungen mit zwischenzeitlich steigenden Amplituden während der Kommutierung und die Stabilitätsoptimierung von Kommutierungszellen ermöglicht. Dafür werden geeignete Modelle der Leistungshalbleiter und der Halbleiterumgebung benötigt. Verhaltensmodelle von Leistungs-MOSFETs und Schottky-Dioden werden für die relevanten Betriebsbedingungen abgeleitet. Die Kombination von Curve-Tracer- und Kurzschlussmessungen ermöglicht die statische Parametrierung des MOSFET-Models für den betrachteten Betriebsbereich. Es wird gezeigt, dass die Kapazitäten des MOSFET-Models aus dynamischen Messungen extrahiert werden können und dass diese Kapazitäten zu einer besseren Übereinstimmung von Messungen und Simulationen führen als die Kapazitäten, die entsprechend der DIN IEC 747 gemessen wurden. Die parasitären Eigenschaften von Gehäusen und Leiterplatten werden mit Koppelkapazitäten und effektiven Widerständen und Induktivitäten modelliert. Mit Hilfe der Finite-Elemente- und der Randelemente-Methode werden die Modellparameter bestimmt. Die entwickelten Verhaltensmodelle der Halbleiter und der elektrischen Verbindungen sowie einfache Modelle des Zwischen-, Treiber- und Lastkreises werden zum Modell des Tiefsetzstellers zusammengefügt. Das Modell kann mit den gemessenen bzw. berechneten Kennlinienfeldern und Parametern das Schaltverhalten des MOSFETs nachbilden. Für die relevanten Arbeitspunkte des Tiefsetzstellers werden Kleinsignalersatzschaltbilder ermittelt. Es wird gezeigt, dass die Stabilitätsanalyse der Kleinsignalersatzschaltbilder die Vorhersage von parasitären Schwingungen mit zwischenzeitlich steigenden Amplituden während der Kommutierung ermöglicht. Maßnahmen zur Stabilitätsoptimierung der Kommutierungszelle werden aus den Ergebnissen der Stabilitätsanalyse von verschiedenen Parametrierungen abgeleitet. Designiterationen und Entwicklungskosten können so reduziert werden.Auch im Buchhandel erhältlich: Analysis of Parasitic Oscillations in Commutation Cells with High Voltage Power MOSFETs / Vera van Treek Ilmenau : ISLE 2014. - xiii, 237 S. ISBN 978-3-938843-79-