Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization. This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values

Proton Damage Effects on Carbon Nanotube Field-Effect Transistors

This research investigated the effects of proton damage on single-walled carbon nanotube (SWCNT) transistors. The transistors were irradiated by 1.8 MeV protons to determine the damage induced in the SWCNTs and the device substrate using Raman spectroscopy, and to observe the effect on transistor functionality by measuring current-voltage characteristics. Irradiation of the SWCNT transistors to a fluence of 1x1013 protons/cm2 resulted in 67% increase in the Raman D/G peak intensity ratio, while at a fluence of 2x1013 protons/cm2 the increase in the D/G ratio was only 18%, likely due to radiation annealing. Current-voltage measurements indicated an increasingly negative threshold voltage shift in SWCNT transistors as a function of proton fluence: -1.3 V after a fluence of 1x1012 protons/cm2 and -1.9 V after a fluence of 2x1013 protons/cm2. The drain current decreased 33% after a fluence of 1x1012 protons/cm2 and 58% after a fluence of 2x1013 protons/cm2. Charge pumping of the SWCNT transistors revealed a significant error attributed to the combination of the non-uniform distribution of SWCNTs across the gate region, adsorbates on the exposed SWCNT and gate oxide surfaces, and inconsistency in transistor performance. The transistor hysteresis also increased as a function of the proton fluence due to interface and bulk charge trapping. This research provided insight into the effect on SWCNT transistors due to proton irradiations up to a fluence of 2x1013 protons/cm2 demonstrating both interface and bulk damage effects

An investigation on border traps in III-V MOSFETs with an In0.53Ga0.47As channel

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device timeto-failure projection

Ion-Beam-Induced Defects in CMOS Technology: Methods of Study

Ion implantation is a nonequilibrium doping technique, which introduces impurity atoms into a solid regardless of thermodynamic considerations. The formation of metastable alloys above the solubility limit, minimized contribution of lateral diffusion processes in device fabrication, and possibility to reach high concentrations of doping impurities can be considered as distinct advantages of ion implantation. Due to excellent controllability, uniformity, and the dose insensitive relative accuracy ion implantation has grown to be the principal doping technology used in the manufacturing of integrated circuits. Originally developed from particle accelerator technology, ion implanters operate in the energy range from tens eV to several MeV (corresponding to a few nms to several microns in depth range). Ion implantation introduces point defects in solids. Very minute concentrations of defects and impurities in semiconductors drastically alter their electrical and optical properties. This chapter presents methods of defect spectroscopy to study the defect origin and characterize the defect density of states in thin film and semiconductor interfaces. The methods considered are positron annihilation spectroscopy, electron spin resonance, and approaches for electrical characterization of semiconductor devices

Development of electrical characterization techniques for lifetime prediction and understanding defects in InGaAs-based III-V transistors

Combining the advanced complementary metal-oxide-semiconductor (CMOS) technique, faster and highly packaged circuits have continuous developing for more than fifty years. During this period time, engineers focus on the higher electrical field and accelerate the degradation to make the highly performance of advanced CMOS devices with better and smaller size than before. At this moment, there are plenty of issues are found which can affect the performances ofthe device. For example, for the new material technique, people prefe tor use III-V materials to instead of the traditional silicon, and for the traditional CMOS device, the main reliability issue is bias temperature instability (BTI), NBTI for pMOS and PBTI for nMOS. Therefore, this thesis will talk about investigating the NBTI/PBTI and III-V device performance and lifetime prediction issues. For the whole ofthe thesis, it can be divided by 4 chapters to describe the details, the first chapter would be the introduction of background knowledge and current understanding for how the traditional CMOS device works, and why the new materials could be instead, like III-V device, it shows the advantages and disadvantages for each of them. Moreover, there are some other information would be explained, such as Discharging-based multiple pulse (DMP) method, and hot carrier stress. Those are also topics and directions relate tod this thesis for the further research. Chapter 2 shows a new measurement method, which called Fast reliability screening technique method (VSS). It compared the conventional measurement method, which is constant voltage stress (CVS), is faster and only use a single device. And it also combined the measurement details and results to show that method is more efficiently, which includes the benefits and parameters discussion in the different conditions. Chapter 3 shows a separation traps method of III-V devices with in In0.53Ga0.47As channel. In this chapter, firstly, it shows the introduction of III-V devices for the basic theory and working function, then there are some experiments, which include both AC and DC measurements to show the III-V devices have very fast recovery abilities. Then because of the recovery ability, the devices would work well after charging and discharging even after heavily stress and long stress time. Moreover, combine the different discharge voltage levels to get the whole border trap energy distribution. After that, the chapter 3 shows how to separate the traps into two different types, type A and type B. there are experiments results and details to show how it is divided. Then it also mentioned the method can work with different stress time, channel thickness and temperature dependence. In Chapter 4, the discussion and a summary about previous work has been given, which also points out the future research plans and directions. It includes the lifetime prediction under slow and fast measurements for III-V devices

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Low Frequency Noise Modeling in Single- and Double-Gate MOSFETs

The Flicker or 1// noise dominates the noise spectrum at low frequency. A serious concern for MOSFETs for circuit application is much higher flicker (1//) noise because of the heterogeneous interface between silicon (Si) and silicon dioxide (Si02). Very high intrinsic flicker noise of CMOS transistors becomes a drawback for low-Intermediate Frequency (IF) or direct-conversion architectures. In spite of extensive research and efforts to understand the low-frequency noise origin in semiconductor devices, there exists no unique theory to explain the low-frequency noise generation mechanism. Flicker noise in MOSFETs is usually perceived to be caused by carrier density fluctuations, which is result of interaction of free carriers with oxide traps via interface states. The most widely accepted theories to explain the flicker noise generation mechanism in MOSFETs are the number fluctuation model proposed by McWhorter based on the tunneling transitions between traps in the oxide and channel carriers, and the mobility fluctuation model, which is described by Hooge\u27s empirical relation. Correlated low frequency noise models, which incorporate both the number fluctuation and correlated surface mobility fluctuation, have also been studied. This work presents a physics-based, analytical model for low-frequency or 1// noise in single- and double-gate MOSFETs. The model is an extension of a correlated low frequency noise model. The developed model takes into account the effects of quantization in the silicon channel, short channel characteristics of the device, and effective trap levels contributing to lowfrequency noise generation mechanism. The inclusion of quantum effects is based on a self-consistent solution of Poisson and Schrbdinger equations in the silicon inversion layer. For low-frequency noise calculation, both the number induced and correlated mobility-induced perturbations caused by the channel carriers\u27 interactions with the oxide states are considered. The physical parameter, effective oxide trap levels at the semiconductor-insulator interface, is modeled using the Hooge parameter and is correlated with inversion charge of the device. The model has been used to predict the low-frequency noise characteristics of a single-gate (bulk) device, a single-gate (SOI) device and a double-gate (SOI) device

ランダム・テレグラフ・ノイズの微細MOSFETへの影響に関する研究

筑波大学 (University of Tsukuba)201