A Parametric Technique for Traps Characterization in AlGaN/GaN HEMTs

A new parametric and cost-effective tech- nique is developed to decouple the mechanisms behind current degradation in AlGaN/GaN HEMTs under a nor- mal device operation: self-heating and charge trapping. A unique approach that investigates charge trapping using both source (IS) and drain (ID) transient currents for the first time. Two types of charge trapping mechanisms are identified: (i) bulk charge trapping occurring on a time scale of less than 1 ms, followed by (ii) surface charge trapping with a time constant larger than a millisecond. Through monitoring the difference between IS and ID, a bulk charge trapping time constant is found to be independent of both drain (VDS ) and gate (VGS ) biases. Surface charge trapping is found to have a much greater impact on a slow degrada- tion when compared to bulk trapping and self-heating. At a short timescale ( 1 ms), the dynamic ON resistance degradation is predominantly limited by surface charge trapping

Characterization of the Dynamic RON of 600 V GaN Switches under Operating Conditions

High-voltage GaN switches can offer tremendous advantages over silicon counterparts for the development of high-efficiency switching-mode power converters at high commutation frequency. Nonetheless, GaN devices are prone to charge-trapping effects that can be particularly relevant in the early-stage development of new technologies. Charge-trapping mechanisms are responsible for the degradation of the dynamic ON-resistance (RON) with respect to its static value: this degradation is typically dependent on the blocking voltage, the commutation frequency and temperature, and is responsible for the reduction of power converter efficiency. The characterization of this phenomenon is very valuable for the development of a new process to compare different technological solutions or for the final assessment of performance. This characterization cannot be made with traditional static or small signal measurements since RON degradation is triggered by application-like dynamic device excitations. In this paper, we propose a technique for the characterization of the dynamic RON of high-voltage GaN switches under real operating conditions: this technique is based on the design of a half bridge switching leg in which the DUT is operated under conditions that resemble its operation in a power converter. With this setup, the characterization of a 600 V GaN switch dynamic RON is performed as a function of variable blocking voltages and commutation frequency. Additionally, this technique allows the separation of thermal and trapping effects, enabling the characterization of the dynamic RON at different temperature

GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs

GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ( \u3c 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition

Device physics and failure mechanisms of deep submicron gate GaN HEMTs for microwave and millimeter-wave applications

openThis thesis presents the findings of a comprehensive characterization study on GaN-based, gate-scaled HEMTs (with Lg < 0.15 µm) for RF applications. The investigation considers performance, stability, and reliability aspects. Specifically, static and dynamic measurements were conducted for the devices under test to assess the influence of short-channel effects and deep-level traps on their characteristics. This involved double-pulse measurements both in OFF and semi-ON state stress and transient measurements. The observed results are compared with those reported in the literature to determine the nature and location of traps responsible for performance variations. In the end stress test were performed to investigate the reliability of the devices. This research contributes to a deeper understanding of the underlying mechanisms and provides valuable insights for the optimization of future GaN-based device designs.This thesis presents the findings of a comprehensive characterization study on GaN-based, gate-scaled HEMTs (with Lg < 0.15 µm) for RF applications. The investigation considers performance, stability, and reliability aspects. Specifically, static and dynamic measurements were conducted for the devices under test to assess the influence of short-channel effects and deep-level traps on their characteristics. This involved double-pulse measurements both in OFF and semi-ON state stress and transient measurements. The observed results are compared with those reported in the literature to determine the nature and location of traps responsible for performance variations. In the end stress test were performed to investigate the reliability of the devices. This research contributes to a deeper understanding of the underlying mechanisms and provides valuable insights for the optimization of future GaN-based device designs