Interpretation of MOS transistor mismatch signature through statistical device simulations

It is impossible to fabricate two exactly identical transistors. Microscopic device architecture differences lead to slightly different electrical performance, indicated with the term mismatch. Due to the shrinking of the device (more pronounced mismatch), the characterization and modeling of the mismatch became one of the most important part of contemporary chip fabrication/design process. \ud In this thesis, MOS transistor mismatch was studied through statistical device simulations. In particular, simulated and measured mismatch signatures have been compared. Mismatch signatures are the combination of the standard deviation of the relative drain current mismatch fluctuation over the full bias range and the correlation of the drain current mismatch at any gate bias with the one observed at threshold voltage. These signatures not only allow a quantitative and qualitative analysis but are also suitable for highlighting subtleties that would be overlooked with a purely quantitative approach. \ud In this thesis, it was demonstrated that interface states between the gate oxide and silicon, if randomized in terms of concentration, energy and position can heavily contribute to the mismatch in the subthreshold region. Moreover, it is shown that the current modeling approach is not able to reproduce the measured signature.\ud The simulation and analysis method, based on mismatch signatures, were applied to study the mismatch behavior of a different type of device: a Lateral Diffused MOS. These devices show a larger mismatch than bulk MOS theory predicts. It was demonstrated that these devices are heavily affected by interface state fluctuations due to their laterally non-uniform doped channel and that measurements can be seriously hampered by series resistance fluctuations.\ud Furthermore, the impact of temperature on mismatch has been studied with extensive measurements across four technology nodes and two channel types and dimensions. Although the main indicators of the MOS transistor mismatch performance, do not vary significantly with temperature, the mismatch in subthreshold changes substantially and the relative ION mismatch of individual matched pair can drift. These previously unreported observations imply that circuit designs employing mismatch compensation techniques should adjust the compensation upon a temperature change.\ud All major findings and outlook for future work are summarized in the conclusive chapter.\u

On the design and characterization of femtoampere current-mode circuits

In this paper, we show and validate a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes. The technique involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents. It also uses a special on-chip sawtooth oscillator to monitor and measure currents down to a few femtoamperes. This way, subpicoampere currents are characterized without driving them off chip and requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is Implemented that uses a 100-fF capacitor and a 3.5-fA bias current to achieve a cutoff frequency of 0.5 Hz. A technique for characterizing noise at these currents is also described and verified. Finally, transistor mismatch measurements are provided and discussed. Experimental measurements are shown throughout the paper, obtained from prototypes fabricated in the AMS 0.35-μm three-metal two-poly standard CMOS process.Ministerio de Ciencia y Tecnología TIC-1999-0446-C02-02, FIT-070000-2001-0859, TIC-2000-0406-P4-05, TIC-2002-10878-EEuropean Union IST-2001-3412

Compact low-power calibration mini-DACs for neural arrays with programmable weights

This paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumptions, a necessity when building large size arrays. One important drawback of weak inversion operation is poor matching between transistors. The resulting effective precision of a fabricated array of 50 DACs turned out to be 47% (1.1 bits), due to transistor mismatch. However, it is possible to combine them two by two in order to build calibrated DACs, thus compensating for inter-DAC mismatch. It is shown experimentally that the precision can be improved easily by a factor of 10 (4.8% or 4.4 bits), which makes these DACs viable for low-resolution applications such as massive arrays of neural processing circuits. A design methodology is provided, and illustrated through examples, to obtain calibrated mini-DACs of a given target precision. As an example application, we show simulation results of using this technique to calibrate an array of digitally controlled integrate-and-fire neurons.Gobierno de España TIC1999-0446-C02-02, TIC2000-0406-P4-05, FIT-07000/2002/921, TIC2002-10878-EEuropean Union IST- 2001-3412

Analog Circuits in Ultra-Deep-Submicron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena

Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology

Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific Medical—ISM—band. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version

An ART1 microchip and its use in multi-ART1 systems

Recently, a real-time clustering microchip neural engine based on the ART1 architecture has been reported. Such chip is able to cluster 100-b patterns into up to 18 categories at a speed of 1.8 μs per pattern. However, that chip rendered an extremely high silicon area consumption of 1 cm2, and consequently an extremely low yield of 6%. Redundant circuit techniques can be introduced to improve yield performance at the cost of further increasing chip size. In this paper we present an improved ART1 chip prototype based on a different approach to implement the most area consuming circuit elements of the first prototype: an array of several thousand current sources which have to match within a precision of around 1%. Such achievement was possible after a careful transistor mismatch characterization of the fabrication process (ES2-1.0 μm CMOS). A new prototype chip has been fabricated which can cluster 50-b input patterns into up to ten categories. The chip has 15 times less area, shows a yield performance of 98%, and presents the same precision and speed than the previous prototype. Due to its higher robustness multichip systems are easily assembled. As a demonstration we show results of a two-chip ART1 system, and of an ARTMAP system made of two ART1 chips and an extra interfacing chip

Fast, non-monte-carlo estimation of transient performance variation due to device mismatch

This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency. The proposed method models DC random offsets as equivalent AC pseudo-noises and leverages the fast, linear periodically time-varying (LPTV) noise analysis available from RF circuit simulators. Therefore, the method can be considered as an extension to DC match analysis and offers a large speed-up compared to the traditional Monte-Carlo analysis. Although the assumed linear perturbation model is valid only for small variations, it enables easy ways to estimate correlations among variations and identify the most sensitive design parameters to mismatch, all at no additional simulation cost. Three benchmarks measuring the variations in the input offset voltage of a clocked comparator, the delay of a logic path, and the frequency of an oscillator demonstrate the speed improvement of about 100-1000x compared to a 1000-point Monte-Carlo method

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator

Mismatch distance term compensation in centroid configurations with nonzero-area devices

This paper presents an analytical approach to distance term compensation in mismatch models of integrated devices. Firstly, the conditions that minimize parameter mismatch are examined under the assumption of zero-area devices. The analytical developments are illustrated using centroid configurations. Then, deviations from the previous approach due to the nonzero device areas are studied and evaluated