Mobility engineering and metal-insulator transition in monolayer MoS2

Two-dimensional (2D) materials are a new class of materials with interesting physical properties and ranging from nanoelectronics to sensing and photonics. In addition to graphene, the most studied 2D material, monolayers of other layered materials such as semiconducting dichalcogenides MoS2 or WSe2 are gaining in importance as promising insulators and channel materials for field-effect transistors (FETs). The presence of a direct band gap in monolayer MoS2 due to quantum mechanical confinement, allows room-temperature field-effect transistors with an on/off ratio exceeding 108. The presence of high-k dielectrics in these devices enhanced their mobility, but the mechanisms are not well understood. Here, we report on electrical transport measurements on MoS2 FETs in different dielectric configurations. Mobility dependence on temperature shows clear evidence of the strong suppression of charge impurity scattering in dual-gate devices with a top-gate dielectric together with phonon scattering that shows a weaker than expected temperature dependence. High levels of doping achieved in dual-gate devices also allow the observation of a metal-insulator transition in monolayer MoS2. Our work opens up the way to further improvements in 2D semiconductor performance and introduces MoS2 as an interesting system for studying correlation effects in mesoscopic systems.Comment: Submitted January 11, 201

Silicon-germanium BiCMOS device and circuit design for extreme environment applications

Silicon-germanium (SiGe) BiCMOS technology platforms have proven invaluable for implementing a wide variety of digital, RF, and mixed-signal applications in extreme environments such as space, where maintaining high levels of performance in the presence of low temperatures and background radiation is paramount. This work will focus on the investigation of the total-dose radiation tolerance of a third generation complementary SiGe:C BiCMOS technology platform. Tolerance will be quantified under proton and X-ray radiation sources for both the npn and pnp HBT, as well as for an operational amplifier built with these devices. Furthermore, a technique known as junction isolation radiation hardening will be proposed and tested with the goal of improving the SEE sensitivity of the npn in this platform by reducing the charge collected by the subcollector in the event of a direct ion strike. To the author's knowledge, this work presents the first design and measurement results for this form of RHBD.M.S.Committee Chair: Cressler, John; Committee Member: Papapolymerou, John; Committee Member: Ralph, Stephe

8x8 Reconfigurable quantum photonic processor based on silicon nitride waveguides

The development of large-scale optical quantum information processing circuits ground on the stability and reconfigurability enabled by integrated photonics. We demonstrate a reconfigurable 8x8 integrated linear optical network based on silicon nitride waveguides for quantum information processing. Our processor implements a novel optical architecture enabling any arbitrary linear transformation and constitutes the largest programmable circuit reported so far on this platform. We validate a variety of photonic quantum information processing primitives, in the form of Hong-Ou-Mandel interference, bosonic coalescence/anticoalescence and high-dimensional single-photon quantum gates. We achieve fidelities that clearly demonstrate the promising future for large-scale photonic quantum information processing using low-loss silicon nitride.Comment: Added supplementary materials, extended introduction, new figures, results unchange

Proceedings of the Cold Electronics Workshop

The benefits and problems of the use of cold semiconductor electronics and the research and development effort required to bring cold electronics into more widespread use were examined

Characterization of self-heating effects and assessment of its impact on reliability in finfet technology

The systematically growing power (heat) dissipation in CMOS transistors with each successive technology node is reaching levels which could impact its reliable operation. The emergence of technologies such as bulk/SOI FinFETs has dramatically confined the heat in the device channel due to its vertical geometry and it is expected to further exacerbate with gate-all-around transistors. This work studies heat generation in the channel of semiconductor devices and measures its dissipation by means of wafer level characterization and predictive thermal simulation. The experimental work is based on several existing device thermometry techniques to which additional layout improvements are made in state of the art bulk FinFET and SOI FinFET 14nm technology nodes. The sensors produce excellent matching results which are confirmed through TCAD thermal simulation, differences between sensor types are quantified and error bars on measurements are established. The lateral heat transport measurements determine that heat from the source is mostly dissipated at a distance of 1µm and 1.5µm in bulk FinFET and SOI FinFET, respectively. Heat additivity is successfully confirmed to prove and highlight the fact that the whole system needs to be considered when performing thermal analysis. Furthermore, an investigation is devoted to study self-heating with different layout densities by varying the number of fins and fingers per active region (RX). Fin thermal resistance is measured at different ambient temperatures to show its variation of up to 70% between -40°C to 175°C. Therefore, the Si fin has a more dominant effect in heat transport and its varying thermal conductivity should be taken into account. The effect of ambient temperature on self-heating measurement is confirmed by supplying heat through thermal chuck and adjacent heater devices themselves. Motivation for this work is the continuous evolution of the transistor geometry and use of exotic materials, which in the recent technology nodes made heat removal more challenging. This poses reliability and performance concerns. Therefore, this work studies the impact of self-heating on reliability testing at DC conditions as well as realistic CMOS logic operating (AC) conditions. Front-end-of-line (FEOL) reliability mechanisms, such as hot carrier injection (HCI) and non-uniform time dependent dielectric breakdown (TDDB), are studied to show that self-heating effects can impact measurement results and recommendations are given on how to mitigate them. By performing an HCI stress at moderate bias conditions, this dissertation shows that the laborious techniques of heat subtraction are no longer necessary. Self-heating is also studied at more realistic device switching conditions by utilizing ring oscillators with several densities and stage counts to show that self-heating is considerably lower compared to constant voltage stress conditions and degradation is not distinguishable

All-Optical Modulation in a Silicon Waveguide Based on a Single-Photon Process

All-optical, low-power modulation is a major goal in photonics. Because of their high mode-field concentration and ease of manufacturing, nanoscale silicon waveguides offer an intriguing platform for photonics. So far, all-optical modulators built with silicon photonic circuits have relied on either two-photon absorption or the Kerr effect. Both effects are weak in silicon, and require extremely high (~5 W) peak optical power levels to achieve modulation. Here, we describe an all-optical Mach-Zehnder modulator based on a single-photon absorption (SPA) process, fabricated entirely in silicon. Our SPA modulator is based on a process by which a single photon at 1.55 mum is absorbed and an apparently free-carrier-mediated process causes an index shift in silicon, even though the photon energy does not exceed that of silicon's bandgap. We demonstrate all-optical modulation with a gate response of 1deg/mW at 0.5 Gb/s. This is over an order of magnitude more responsive than typical previously demonstrated devices. Even without resonant enhancement, further engineering may enable all optical modulation with less than 10 mW of gate power required for complete extinction, and speeds of 5 Gb/s or higher