Photodiodes and Image Sensors on Mechanically Flexible Ultra-Thin Silicon Chips-in-Foil

CMOS-Bildsensoren haben in den letzten zwei Jahrzehnten enorme technologische Fortschritte erfahren und sich als eine wettbewerbsfähige Alternative gegenüber CCDBildsensoren auf dem Markt etabliert. Reduziert man die Chipdicke von CMOSBildsensoren von normal 725 μm auf ≤ 30 μm, erhält man mechanisch flexible Bildaufnehmer. Gewölbte CMOS-Bildsensoren würden für die optische Wahrnehmung völlig neue Möglichkeiten eröffnen (wie z. B. bei Insektenaugen). Betrachtet man die auf dem Chip integrierten Bauelemente und Schaltungen unter mechanischen Spannungen, stellt man fest, dass ihre elektrischen und optoelektronischen Eigenschaften von der ausgeübten mechanischen Spannung beeinflusst werden. Für den technischen Einsatz ist eine vom mechanischen Zustand des Bildsensors unbeinflusste Funktion erforderlich. Der Einfluss von mechanischer Spannung auf die Bauelemente- und Schaltungs-Charakteristiken und seine Minimierung bzw. Kompensation sind daher von besonderem Interesse. In dieser Arbeit wurden die optischen und elektrischen Eigenschaften von passiven und aktiven Bauelementen, sowie integrierten Schaltungen auf monokristallinen gedünnten flexiblen Siliziumchips unter mechanischen Spannungen untersucht. Der Einfluss von mechanischen Spannungen auf optische Eigenschaften (spektrale Lichtempfindlichkeit, Dunkelstrom und elektronisches Rauschen) einzelner p-n-Übergang basierter Photodioden und Bildsensorarrays auf (100)-Siliziumwafern wurde theoretisch modelliert und experimentell charakterisiert. Weiterhin wurden die elektrischen Eigenschaften (Ladungsträgerbeweglichkeit, Schwellenspannung, 1/f Rauschen) von MOSFeldeffekttransistoren in Bezug auf mechanischen Spannungen charakterisiert und ihre Abhängigkeit von der Orientierung zur Kristallorientierung des Substrats untersucht. Integrierte Schaltungen, wie Bandgap-Referenzspannungsquellen, Operationsverstärker und SC-basierte Schaltungen wurden unter mechanischen Spannungen theoretisch betrachtet, entworfen, gefertigt und experimentell charakterisiert. Mit Hilfe des in dieser Arbeit vorgeschlagenen und eingesetzten Simulationskonzeptes, ist die Schaltungssimulation der obengenannten Abhängigkeiten möglich. Dadurch hat der Schaltungsentwickler die Möglichkeit Schaltungskonzepte zur Kompensation oder Minimierung der von der mechanischen Spannung hervorgerufenen Einflüsse zu simulieren. In dieser Hinsicht werden Schaltungskonzepte und Design-Regeln präsentiert, die den Einfluss von mechanischen Spannungen auf Bildsensorchips berücksichtigen und minimieren. Im Rahmen dieser Arbeit wurde darüber hinaus ein mechanisch flexibler Bildsensorchip entworfen, simuliert und gefertigt, dessen Betrieb unabhängig von der ausgeübten mechanischen Spannung ist. Der ultra-dünne 20 μm Bildsensorchip ist geeignet auf zylindrisch gewölbte Oberflächen aufgebracht zu werden und erlaubt die Aufnahme raumrichtungsselektiver optischer Informationen im Sinne eines Panoramablicks.CMOS image sensors (CIS) have experienced the last two decades tremendous technological advances rendering them a viable alternative to charged couple devices (CCDs) not only in high volume applications but also in applications which require high spatial and temporal resolution, high dynamic range, low noise or high sensitivity levels. CISs are employed due to their increased chip thickness (ca. 750 μm) solely in the traditional planar image acquisition. If the chip thickness could be reduced down to or less than 30 μm, the silicon chips would become mechanically flexible. Such flexible CISs could substantially extend the application spectrum of image sensors in non-conventional imaging systems (e.g. imitating insect vision). However, the on-chip integrated devices and circuits exhibit stress-induced changes on their electrical and optoelectronic characteristics. Since a stress independent operation is striven, the minimization or compensation of the influence of mechanical stress on the characteristics of devices and circuits is of great interest. In this work optical and electrical properties of passive and active devices as well as integrated circuits on ultra-thin monolithic flexible silicon chips have been investigated under the application of mechanical stress. The influence of mechanical stress on the optical characteristics (spectral sensitivity, dark current and electronic noise) of p-n junction based photodiodes and image sensor chips on (100)-silicon wafers have been theoretically modeled and experimentally characterized. Moreover, the electrical characteristics (carrier mobility, threshold voltage and 1/f noise) of mechanically strained MOS field-effect transistors and their dependence on the channel orientation on the substrate have been investigated. Integrated circuits such as bandgap reference voltage sources, operational amplifiers and switched capacitor (SC) based circuits have been theoretically treated, designed, fabricated and experimentally characterized. Within this framework a simulation technique has been proposed and deployed, which allows the simulation of the above mentioned stress dependence on device and circuit level. The analog circuit designer can employ the simulation technique toward the proposal of circuit topologies or techniques, which minimize or compensate the strain-induced changes on the circuit operation. In this direction, circuit concepts and design rules are proposed, which minimize the influence of mechanical stress on flexible CIS chips. Within the scope of this work, a mechanically flexible CMOS image sensor chip has been designed, simulated and fabricated, which operation is stress independent. The developed ultra-thin 20 μm CIS chip can be wrapped around a cylindrically curved surface and thus record panoramic optical information

DEFECTS AND LIFETIME PREDICTION OF GERMANIUM MOSFETS

To continue improving device speed, much effort has been made to replace Si by high mobility semiconductors. Ge is considered as a strong candidate for pMOSFETs due to the high hole mobility. Two approaches have been demonstrated: high-k/Si-cap/Ge and high-k/GeO2/Ge. Negative Bias Temperature Instability (NBTI) is still one of the main reliability issues, limiting the device lifetime. In this project, it is found that the conventional lifetime prediction method developed for Si is inapplicable to Ge devicesand defect properties in Ge and Si MOSFETs are different.The threshold voltage degradation in Ge can be nearly 100% recovered under a much lower temperature than that in Si devices. The defect losses observed in Si devices were absent in Ge/GeO2/Al2O3. The generation of interface states is insignificant and the positive charges in GeO2/Al2O3 on Ge dominate the NBTI. These positive charges do not follow the same model as those in SiON/Si and an energy-alternating model has been proposed: there are a spread of energy levels of neutral hole traps below Ev andthey lift up after charging, and return below Ev after neutralization.The energy distribution of positive charges in the Al2O3/GeO2/Ge gate stack was studied by the Discharge-based Multi-pulse (DMP) Technique. The different stress-time dependence of defects below Ev and around Ec indicates that they originate from different defects. Quantization effect, Fermi level pinning, and discharge voltage step were considered. The defect differences in terms of the energy level were investigated by using the DMP technique and the energy alternating model is verified by the defect energy distribution.Based on the understanding of different defect behavior, a new NBTI lifetime prediction method was developed for Ge MOSFETs. Energy alternating defects were separated from as-grown hole traps (AHT), which enables to restore the power law for NBTI kinetics with a constant power exponent. The newly developed Ge method was applicable for NBTI lifetime prediction of the state-of-the-art Si-cap/Ge and GeO2/Ge MOSFETs. When compared with SiON/Si, the optimized Si-cap/Ge shows superior reliability, while GeO2/Ge is inferior and needs further optimization. Preliminary characterization was also carried out to investigate the impacts of energy levels and characteristic times of different defects on the frequency and duty factor dependence of AC NBTI degradation

pMOSFET fabrication using a low temperature pre-deposition technique

The objective of this work was to develop a fully functional pMOSFET using a new method for dopant pre-deposition done at low temperature (90ºC) using PECVD. This technique has many advantages when compared to the traditional manufacturing method, namely it is more cost effective, simpler and faster. Because it does not require an oxide layer to create the patterns, it can be conjugated with other low temperature techniques. To obtain a functional pMOSFET, this work was divided in four different studies. The objective of the first study was to achieve metal-semiconductor ohmic contacts. To obtain a perfect ohmic contact of aluminum in a n-type silicon wafer, it is necessary to create a narrow space-charge region in order to allow carrier tunneling. That was reached by using a highly doped n-type hydrogenated amorphous silicon thin film made with a phosphine gas phase concentration of 1.5%, followed by a one-hour diffusion process at 1000ºC. A sheet resistance of 22.9 Ω/□ and a phosphorus surface concentration of 5.2 × 1019 aṫ cm-3 were obtained. The second study consisted of producing p+n junctions varying the surface concentration and the diffusion time and temperature. The best diodes produced have significantly different profiles. The first was produced with a deep junction and a 0.165% diborane in the gas phase and presents the following parameters: rectification ratio of 6.01 × 103, threshold voltage of 0.53 V and an ideality factor of 1.74. The second diode was produced with a shallow junction and using a 1.5% diborane in the gas phase with the parameters: rectification ration of 3.94 × 103, a threshold voltage of 0.46 V and an ideality factor of 2.58. Regarding the oxide characteristics for application as gate dielectric (third study), it was determined that the best oxides were produced by wet oxidation with a thickness of about 1300 Å. After finishing the previous studies, it was possible to produce a fully functional p-type field effect transistor (fourth study). The MOSFETs worked in enhancement mode with the best parameters being: a threshold voltage of -4 V and a field effect mobility of 106.56 cm2/Vs

Remote plasma chemical vapor deposition for high efficiency heterojunction solar cells on low cost, ultra-thin, semiconductor-on-metal substrates

textIn the crystalline Si solar cell industry, there is a push to reduce module cost through a combination of thinner substrates and increased cell efficiency. Achieving solar cells with sub-100 µm substrates cost-effectively is a formidable task because such thin substrates impose stringent handling requirements and thermal budget due to their flexibility, ease of breakage, and low yield. Moreover, as the substrate thickness decreases the surface passivation quality dictates the performance of the cells. Crystalline Si heterojunction (HJ) solar cells based on hydrogenated amorphous silicon (a-Si:H) have attracted significant interest in recent years due to their excellent surface passivation properties, potential for high efficiency, low thermal budget and low cost. HJ cells with ultra-passivated surfaces showing > 700 mV open-circuit voltages (Voc) and > 20% conversion efficiency have been demonstrated. In these cells, it has been identified that high-quality a-Si:H films deposited by a low-damage plasma process is key to achieving such high cell performance. However, the options for low-damage plasma deposition process are limited. The main objectives of this work are to develop a low-plasma damage a-Si:H thin film deposition process based on remote plasma chemical vapor deposition (RPCVD) and to demonstrate high efficiency HJ solar cells on bulk substrates as well as on ultra-thin silicon and germanium substrates obtained by a novel, low-cost semiconductor-on-metal (SOM) technology. This manuscript presents a detailed description of the RPCVD system and the process leading to the realization of high quality a-Si:H thin films and high efficiency HJ solar cells. First, p-type a-Si:H thin films are developed and optimized, then HJ solar cells are subsequently fabricated on bulk and ultra-thin Si and Ge SOM substrates without intrinsic a-Si:H passivation. Single HJ cells on ~ 500 µm bulk Si and ~25 µm ultra-thin substrates exhibited conversion efficiencies of η = 16% (Voc = 615 mV, Jsc = 34 mA/cm2, and FF = 77%) and η = 11.2% (Voc = 605 mV, Jsc = 29.6 mA/cm2, and FF = 62.8%), respectively. The performance of the ~25 µm cell was further improved to η = 13.4% (Voc = 645 mV, Jsc = 31.4 mA/cm2, and FF = 66.2%) by implementing the dual HJ architecture without front side i-layer passivation. For single HJ cells based on Ge substrates, the results were η = 1.78 % (Voc = 148 mV, Jsc = 35.1 mA/cm2, and FF = 1.78%) on ~500 µm bulk Ge, compared to η =5.3% (Voc = 203 mV, Jsc = 44.7 mA/cm2, and FF = 5.28%) on ~ 50 µm Ge SOM substrates. Respectively, the results obtained on ultra-thin SOM substrates are among the highest reported in literature for based on comparable architecture and substrate thickness. In order to achieve improved cell performance, dual HJ cells with i-layer passivation of both surfaces were fabricated. First, optimized RPCVD-based i-layer films were developed by varying the deposition temperature and H2 dilution ratio (R). It was found that excellent surface passivation on planar substrates with as-deposited minority carrier lifetimes > 1 ms is achievable by using deposition temperature of 200 ºC and moderate dilution ratio 0.5 ≤ R ≤ 1, even without the more rigorous RCA pre-cleaning process typically used in literature for achieving comparable results. Subsequently, dual HJ solar cells with i-layer films were demonstrated on planar and textured bulk Si substrates showing improved conversion efficiencies of η = 17.3% (Voc = 664 mV, Jsc = 34.34 mA/cm2 and FF = 76%) and η = 19.4% (Voc = 643 mV, Jsc = 38.99 mA/cm2, and FF = 77.5%), respectively.Electrical and Computer Engineerin

Recent Advances in Thin Film Electronic Devices

This reprint is a collection of the papers from the Special Issue “Recent Advances in Thin Film Electronic Devices” in Micromachines. In this reprrint, 1 editorial and 11 original papers about recent advances in the research and development of thin film electronic devices are included. Specifically, three research fields are covered: device fundamentals (5 papers), fabrication processes (5 papers), and testing methods (1 paper). The experimental data, simulation results, and theoretical analysis presented in this reprint should benefit those researchers in flat panel displays, flat panel sensors, energy devices, memories, and so on