138 research outputs found
Design Automation and Application for Emerging Reconfigurable Nanotechnologies
In the last few decades, two major phenomena have revolutionized the electronic industry – the ever-increasing dependence on electronic circuits and the Complementary Metal Oxide Semiconductor (CMOS) downscaling. These two phenomena have been complementing each other in a way that while electronics, in general, have demanded more computations per functional unit, CMOS downscaling has aptly supported such needs. However, while the computational demand is still rising exponentially, CMOS downscaling is reaching its physical limits. Hence, the need to explore viable emerging nanotechnologies is more imperative than ever. This thesis focuses on streamlining the existing design automation techniques for a class of emerging reconfigurable nanotechnologies. Transistors based on this technology exhibit duality in conduction, i.e. they can be configured dynamically either as a p-type or an n-type device on the application of an external bias. Owing to this dynamic reconfiguration, these transistors are also referred to as Reconfigurable Field-Effect Transistors (RFETs).
Exploring and developing new technologies just like CMOS, require tackling two main challenges – first, design automation flow has to be modified to enable tailor- made circuit designs. Second, possible application opportunities should be explored where such technologies can outsmart the existing CMOS technologies. This thesis targets the above two objectives for emerging reconfigurable nanotechnologies by proposing approaches for enabling an Electronic Design Automation (EDA) flow for circuits based on RFETs and exploring hardware security as an application that exploits the transistor-level dynamic reconfiguration offered by this technology.
This thesis explains the bottom-up approach adopted to propose a logic synthesis flow by identifying new logic gates and circuit design paradigms that can particularly exploit the dynamic reconfiguration offered by these novel nanotechnologies. This led to the subsequent need of finding natural Boolean logic abstraction for emerging reconfigurable nanotechnologies as it is shown that the existing abstraction of negative unate logic for CMOS technologies is sub-optimal for RFETs-based circuits. In this direction, it has been shown that duality in Boolean logic is a natural abstraction for this technology and can truly represent the duality in conduction offered by individual transistors. Finding this abstraction paved the way for defining suitable primitives and proposing various algorithms for logic synthesis and technology mapping.
The following step is to explore compatible physical synthesis flow for emerging reconfigurable nanotechnologies. Using silicon nanowire-based RFETs, .lef and .lib files have been provided which can provide an end-to-end flow to generate .GDSII file for circuits exclusively based on RFETs. Additionally, new approaches have been explored to improve placement and routing for circuits based on reconfigurable nanotechnologies. It has been demonstrated how these approaches led to superior results as compared to the native flow meant for CMOS.
Lastly, the unique property of transistor-level reconfiguration offered by RFETs is utilized to implement efficient Intellectual Property (IP) protection schemes against adversarial attacks. The ability to control the conduction of individual transistors can be argued as one of the impactful features of this technology and suitably fits into the paradigm of security measures. Prior security schemes based on CMOS technology often come with large overheads in terms of area, power, and delay. In contrast, RFETs-based hardware security measures such as logic locking, split manufacturing, etc. proposed in this thesis, demonstrate affordable security solutions with low overheads.
Overall, this thesis lays a strong foundation for the two main objectives – design automation, and hardware security as an application, to push emerging reconfigurable nanotechnologies for commercial integration. Additionally, contributions done in this thesis are made available under open-source licenses so as to foster new research directions and collaborations.:Abstract
List of Figures
List of Tables
1 Introduction
1.1 What are emerging reconfigurable nanotechnologies?
1.2 Why does this technology look so promising?
1.3 Electronics Design Automation
1.4 The game of see-saw: key challenges vs benefits for emerging reconfigurable nanotechnologies
1.4.1 Abstracting ambipolarity in logic gate designs
1.4.2 Enabling electronic design automation for RFETs
1.4.3 Enhanced functionality: a suitable fit for hardware security applications
1.5 Research questions
1.6 Entire RFET-centric EDA Flow
1.7 Key Contributions and Thesis Organization
2 Preliminaries
2.1 Reconfigurable Nanotechnology
2.1.1 1D devices
2.1.2 2D devices
2.1.3 Factors favoring circuit-flexibility
2.2 Feasibility aspects of RFET technology
2.3 Logic Synthesis Preliminaries
2.3.1 Circuit Model
2.3.2 Boolean Algebra
2.3.3 Monotone Function and the property of Unateness
2.3.4 Logic Representations
3 Exploring Circuit Design Topologies for RFETs
3.1 Contributions
3.2 Organization
3.3 Related Works
3.4 Exploring design topologies for combinational circuits: functionality-enhanced logic gates
3.4.1 List of Combinational Functionality-Enhanced Logic Gates based on RFETs
3.4.2 Estimation of gate delay using the logical effort theory
3.5 Invariable design of Inverters
3.6 Sequential Circuits
3.6.1 Dual edge-triggered TSPC-based D-flip flop
3.6.2 Exploiting RFET’s ambipolarity for metastability
3.7 Evaluations
3.7.1 Evaluation of combinational logic gates
3.7.2 Novel design of 1-bit ALU
3.7.3 Comparison of the sequential circuit with an equivalent CMOS-based design
3.8 Concluding remarks
4 Standard Cells and Technology Mapping
4.1 Contributions
4.2 Organization
4.3 Related Work
4.4 Standard cells based on RFETs
4.4.1 Interchangeable Pull-Up and Pull-Down Networks
4.4.2 Reconfigurable Truth-Table
4.5 Distilling standard cells
4.6 HOF-based Technology Mapping Flow for RFETs-based circuits
4.6.1 Area adjustments through inverter sharings
4.6.2 Technology Mapping Flow
4.6.3 Realizing Parameters For The Generic Library
4.6.4 Defining RFETs-based Genlib for HOF-based mapping
4.7 Experiments
4.7.1 Experiment 1: Distilling standard-cells from a benchmark suite
4.7.2 Experiment 2A: HOF-based mapping .
4.7.3 Experiment 2B: Using the distilled standard-cells during mapping
4.8 Concluding Remarks
5 Logic Synthesis with XOR-Majority Graphs
5.1 Contributions
5.2 Organization
5.3 Motivation
5.4 Background and Preliminaries
5.4.1 Terminologies
5.4.2 Self-duality in NPN classes
5.4.3 Majority logic synthesis
5.4.4 Earlier work on XMG
5.4.5 Classification of Boolean functions
5.5 Preserving Self-Duality
5.5.1 During logic synthesis
5.5.2 During versatile technology mapping
5.6 Advanced Logic synthesis techniques
5.6.1 XMG resubstitution
5.6.2 Exact XMG rewriting
5.7 Logic representation-agnostic Mapping
5.7.1 Versatile Mapper
5.7.2 Support of supergates
5.8 Creating Self-dual Benchmarks
5.9 Experiments
5.9.1 XMG-based Flow
5.9.2 Experimental Setup
5.9.3 Synthetic self-dual benchmarks
5.9.4 Cryptographic benchmark suite
5.10 Concluding remarks and future research directions
6 Physical synthesis flow and liberty generation
6.1 Contributions
6.2 Organization
6.3 Background and Related Work
6.3.1 Related Works
6.3.2 Motivation
6.4 Silicon Nanowire Reconfigurable Transistors
6.5 Layouts for Logic Gates
6.5.1 Layouts for Static Functional Logic Gates
6.5.2 Layout for Reconfigurable Logic Gate
6.6 Table Model for Silicon Nanowire RFETs
6.7 Exploring Approaches for Physical Synthesis
6.7.1 Using the Standard Place & Route Flow
6.7.2 Open-source Flow
6.7.3 Concept of Driver Cells
6.7.4 Native Approach
6.7.5 Island-based Approach
6.7.6 Utilization Factor
6.7.7 Placement of the Island on the Chip
6.8 Experiments
6.8.1 Preliminary comparison with CMOS technology
6.8.2 Evaluating different physical synthesis approaches
6.9 Results and discussions
6.9.1 Parameters Which Affect The Area
6.9.2 Use of Germanium Nanowires Channels
6.10 Concluding Remarks
7 Polymporphic Primitives for Hardware Security
7.1 Contributions
7.2 Organization
7.3 The Shift To Explore Emerging Technologies For Security
7.4 Background
7.4.1 IP protection schemes
7.4.2 Preliminaries
7.5 Security Promises
7.5.1 RFETs for logic locking (transistor-level locking)
7.5.2 RFETs for split manufacturing
7.6 Security Vulnerabilities
7.6.1 Realization of short-circuit and open-circuit scenarios in an RFET-based inverter
7.6.2 Circuit evaluation on sub-circuits
7.6.3 Reliability concerns: A consequence of short-circuit scenario
7.6.4 Implication of the proposed security vulnerability
7.7 Analytical Evaluation
7.7.1 Investigating the security promises
7.7.2 Investigating the security vulnerabilities
7.8 Concluding remarks and future research directions
8 Conclusion
8.1 Concluding Remarks
8.2 Directions for Future Work
Appendices
A Distilling standard-cells
B RFETs-based Genlib
C Layout Extraction File (.lef) for Silicon Nanowire-based RFET
D Liberty (.lib) file for Silicon Nanowire-based RFET
Modeling and Analysis of Large-Scale On-Chip Interconnects
As IC technologies scale to the nanometer regime, efficient and accurate modeling
and analysis of VLSI systems with billions of transistors and interconnects becomes
increasingly critical and difficult. VLSI systems impacted by the increasingly high
dimensional process-voltage-temperature (PVT) variations demand much more modeling
and analysis efforts than ever before, while the analysis of large scale on-chip
interconnects that requires solving tens of millions of unknowns imposes great challenges
in computer aided design areas. This dissertation presents new methodologies
for addressing the above two important challenging issues for large scale on-chip interconnect
modeling and analysis:
In the past, the standard statistical circuit modeling techniques usually employ
principal component analysis (PCA) and its variants to reduce the parameter
dimensionality. Although widely adopted, these techniques can be very
limited since parameter dimension reduction is achieved by merely considering
the statistical distributions of the controlling parameters but neglecting
the important correspondence between these parameters and the circuit performances
(responses) under modeling. This dissertation presents a variety of
performance-oriented parameter dimension reduction methods that can lead to
more than one order of magnitude parameter reduction for a variety of VLSI
circuit modeling and analysis problems.
The sheer size of present day power/ground distribution networks makes their
analysis and verification tasks extremely runtime and memory inefficient, and
at the same time, limits the extent to which these networks can be optimized.
Given today?s commodity graphics processing units (GPUs) that can deliver
more than 500 GFlops (Flops: floating point operations per second). computing
power and 100GB/s memory bandwidth, which are more than 10X greater
than offered by modern day general-purpose quad-core microprocessors, it is
very desirable to convert the impressive GPU computing power to usable design
automation tools for VLSI verification. In this dissertation, for the first time, we
show how to exploit recent massively parallel single-instruction multiple-thread
(SIMT) based graphics processing unit (GPU) platforms to tackle power grid
analysis with very promising performance. Our GPU based network analyzer
is capable of solving tens of millions of power grid nodes in just a few seconds.
Additionally, with the above GPU based simulation framework, more challenging
three-dimensional full-chip thermal analysis can be solved in a much more
efficient way than ever before
Cycle-accurate modeling of multicore processors on FPGAs
Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (pages 169-176).We present a novel modeling methodology which enables the generation of a high-performance, cycle-accurate simulator from a cycle-level specification of the target design. We describe Arete, a full-system multicore processor simulator, developed using our modeling methodology. We provide details on Arete's resource-efficient and high-performance implementation on multiple FPGA platforms, and the architectural experiments performed using it. We present clear evidence that the use of simplified models in architectural studies can lead to wrong conclusions. Through two experiments performed using both cycle-accurate and simplified models, we show that on one hand there are substantial quantitative and qualitative differences in results, and on the other, the results match quite well.by Asif Imtiaz Khan.Ph.D
Energy-aware synthesis for networks on chip architectures
The Network on Chip (NoC) paradigm was introduced as a scalable communication infrastructure for future System-on-Chip applications. Designing application specific customized communication architectures is critical for obtaining low power, high performance solutions. Two significant design automation problems are the creation of an optimized configuration, given application requirement the implementation of this on-chip network. Automating the design of on-chip networks requires models for estimating area and energy, algorithms to effectively explore the design space and network component libraries and tools to generate the hardware description. Chip architects are faced with managing a wide range of customization options for individual components, routers and topology. As energy is of paramount importance, the effectiveness of any custom NoC generation approach lies in the availability of good energy models to effectively explore the design space. This thesis describes a complete NoC synthesis flow, called NoCGEN, for creating energy-efficient custom NoC architectures. Three major automation problems are addressed: custom topology generation, energy modeling and generation. An iterative algorithm is proposed to generate application specific point-to-point and packet-switched networks. The algorithm explores the design space for efficient topologies using characterized models and a system-level floorplanner for evaluating placement and wire-energy. Prior to our contribution, building an energy model required careful analysis of transistor or gate implementations. To alleviate the burden, an automated linear regression-based methodology is proposed to rapidly extract energy models for many router designs. The resulting models are cycle accurate with low-complexity and found to be within 10% of gate-level energy simulations, and execute several orders of magnitude faster than gate-level simulations. A hardware description of the custom topology is generated using a parameterizable library and custom HDL generator. Fully reusable and scalable network components (switches, crossbars, arbiters, routing algorithms) are described using a template approach and are used to compose arbitrary topologies. A methodology for building and composing routers and topologies using a template engine is described. The entire flow is implemented as several demonstrable extensible tools with powerful visualization functionality. Several experiments are performed to demonstrate the design space exploration capabilities and compare it against a competing min-cut topology generation algorithm
Satisfiability-Based Methods for Digital Circuit Design, Debug, and Optimization
Designing digital circuits well is notoriously difficult. This difficulty stems in part from the very
many degrees of freedom inherent in circuit design, typically coupled with the need to satisfy
various constraints. In this thesis, we demonstrate how formulations of satisfiability problems
can be used automatically to complete a design, or to find a specific design architecture that
satisfies certain constraints; how these can be used to create, debug, and optimize designs;
and introduce a domain-specific language particularly well-suited for satisfiability-assisted
design, debug, and optimization.
In the first application, we show how explicit uncertainties called âholesâ can both be natural
to use and conducive to the creation of formal satisfiability problems useful for designing
circuits. We further develop a Scala-hosted Domain Specific Language (DSL) with appropriate
syntactic sugar to make design with holes easy and effective.
We then show how, utilizing the same kind of satisfiability formulation, we can automatically
instrument a given buggy design to replace suspicious syntax fragments with potentially-correct alternatives. The satisfiability solver then determines if there is any possible set of
alternative fragments which fix the bug. We also demonstrate that this approach is reasonably
scalable, in part because there is less need for a fully-precise specification in the formulation
of the satisfiability problem.
We then advance beyond mere hole-filling and show how a tight integration of design elaboration with satisfiability solvers allows totally new approaches. To point, we use this tight
integration to create the first known methods to optimize Gate-Level Information Flow Track-
ing (GLIFT) model circuits and to make principled trade-offs in their precision.
Finally, integrating all the previous work, we propose a more powerful DSL specifically designed to address the shortcomings of the first âhole-fillingâ language. This language, which
we call Nasadiya, affords more general integrations of satisfiability into circuit design and optimization, and provides built-in modeling functionality useful for optimizing extra-functional
properties like critical path delay and circuit area. We demonstrate the utility of these features
by implementing an automatic power optimizer for a popular type of parallel prefix adders
Driving the Network-on-Chip Revolution to Remove the Interconnect Bottleneck in Nanoscale Multi-Processor Systems-on-Chip
The sustained demand for faster, more powerful chips has been met by the
availability of chip manufacturing processes allowing for the integration of increasing
numbers of computation units onto a single die. The resulting outcome,
especially in the embedded domain, has often been called SYSTEM-ON-CHIP
(SoC) or MULTI-PROCESSOR SYSTEM-ON-CHIP (MP-SoC).
MPSoC design brings to the foreground a large number of challenges, one of
the most prominent of which is the design of the chip interconnection. With a
number of on-chip blocks presently ranging in the tens, and quickly approaching
the hundreds, the novel issue of how to best provide on-chip communication
resources is clearly felt.
NETWORKS-ON-CHIPS (NoCs) are the most comprehensive and scalable
answer to this design concern. By bringing large-scale networking concepts to
the on-chip domain, they guarantee a structured answer to present and future
communication requirements. The point-to-point connection and packet switching
paradigms they involve are also of great help in minimizing wiring overhead
and physical routing issues. However, as with any technology of recent inception,
NoC design is still an evolving discipline. Several main areas of interest
require deep investigation for NoCs to become viable solutions:
• The design of the NoC architecture needs to strike the best tradeoff among
performance, features and the tight area and power constraints of the onchip
domain.
• Simulation and verification infrastructure must be put in place to explore,
validate and optimize the NoC performance.
• NoCs offer a huge design space, thanks to their extreme customizability in
terms of topology and architectural parameters. Design tools are needed
to prune this space and pick the best solutions.
• Even more so given their global, distributed nature, it is essential to evaluate
the physical implementation of NoCs to evaluate their suitability for
next-generation designs and their area and power costs.
This dissertation performs a design space exploration of network-on-chip architectures,
in order to point-out the trade-offs associated with the design of
each individual network building blocks and with the design of network topology
overall. The design space exploration is preceded by a comparative analysis
of state-of-the-art interconnect fabrics with themselves and with early networkon-
chip prototypes. The ultimate objective is to point out the key advantages
that NoC realizations provide with respect to state-of-the-art communication
infrastructures and to point out the challenges that lie ahead in order to make
this new interconnect technology come true. Among these latter, technologyrelated
challenges are emerging that call for dedicated design techniques at all
levels of the design hierarchy. In particular, leakage power dissipation, containment
of process variations and of their effects. The achievement of the above
objectives was enabled by means of a NoC simulation environment for cycleaccurate
modelling and simulation and by means of a back-end facility for the
study of NoC physical implementation effects. Overall, all the results provided
by this work have been validated on actual silicon layout
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