Circuit reliability prediction: Challenges and solutions for the device time-dependent variability characterization roadblock

Copyright IEEEThe characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-Aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.This work was supported by the VIGILANT Project (PID2019-103869RB / AEI / 10.13039/501100011033) and the TEC2016-75151-C3-R Project (AEI/FEDER, UE).Peer reviewe

Liquid-gate 2D material-on-insulator transistors for sensing applications

This research investigates the use of 2D materials (specifically graphene) as active channel in liquid-gate transistors used as detectors of biological targets on functionalized surfaces. However, before these sensors can be effectively used, it is crucial to establish a reliable sensing platform within two-dimensional materials as active channels, and to evaluate the fabrication, lithography, and reliability of these devices. In this study, we analyzed the inter-device variability and reliability of the transistors, as well as the potential factors that may exacerbate these issues under operative conditions. We performed structural characterization to confirm the quality of the materials, followed by photolithography and processing to create liquid-gate sensors. We then conducted electrical evaluations of the devices, which revealed significant reliability issues and inter-device variability. To address these problems, we propose the use of an intergate-coupling effect that utilizes both front- and back-gates simultaneously. Our findings have important implications for the design and optimization of 2D materials-based liquid-gate sensors for biological applications.European Union’s Horizon 2020 research and innovation programme under the MSC grant No 895322Spanish and Andalusian Programs DTS20/00038P18-RT-4826, PYC-020-RE-023UGRA-TIC-628-UGR20PID2020- 119668GB-I00. Funding for open access charge: Universidad de Granada / CBU

6T CMOS SRAM Stability in Nanoelectronic Era: From Metrics to Built-in Monitoring

The digital technology in the nanoelectronic era is based on intensive data processing and battery-based devices. As a consequence, the need for larger and energy-efficient circuits with large embedded memories is growing rapidly in current system-on-chip (SoC). In this context, where embedded SRAM yield dominate the overall SoC yield, the memory sensitivity to process variation and aging effects has aggressively increased. In addition, long-term aging effects introduce extra variability reducing the failure-free period. Therefore, although stability metrics are used intensively in the circuit design phases, more accurate and non-invasive methodologies must be proposed to observe the stability metric for high reliability systems. This chapter reviews the most extended memory cell stability metrics and evaluates the feasibility of tracking SRAM cell reliability evolution implementing a detailed bit-cell stability characterization measurement. The memory performance degradation observation is focused on estimating the threshold voltage (Vth) drift caused by process variation and reliability mechanisms. A novel SRAM stability degradation measurement architecture is proposed to be included in modern memory designs with minimal hardware intrusion. The new architecture may extend the failure-free period by introducing adaptable circuits depending on the measured memory stability parameter

Towards Reliability- & Variability-aware Design-Technology Co-optimization in Advanced Nodes: Defect Characterization, Industry-friendly Modelling and ML-assisted Prediction

Reliability- & variability-aware Design Technology co-optimization (RV-DTCO) becomes indispensable with advanced nodes. However, four key issues hinder its practical adoption: the lack of characterization technique that offer both accuracy and efficiency, the lack of defect model with long-term prediction capability, the lack of compact model compatible with most EDA platforms, and the low efficiency in circuit-level prediction to support frequent iterations during co-optimization. Demonstrating with 7nm technology, this work tackles these issues by developing an efficient characterization method for separating defects, introducing a comprehensive test-data-verified defect-centric physical-based model & an industry-friendly OMI-based compact model, and proposing a machine learning-assisted approach to accelerate circuit-level prediction. With these achievements, a RV-DTCO flow is established and demonstrated on 3nm GAA technology to bridge the material level to the circuit level. The work paves ways in boosting adoption of RV-DTCO in both circuit design & process development for ultimate nodes. Index Terms— Design Technology co-optimization (DTCO), FinFET, reliability, variability, Discharging-based multi-pulse technique (DMP), OMI, ST-GN

A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

RRAM variability and its mitigation schemes

Emerging technologies such as RRAMs are attracting significant attention due to their tempting characteristics such as high scalability, CMOS compatibility and non-volatility to replace the current conventional memories. However, critical causes of hardware reliability failures, such as process variation due to their nano-scale structure have gained considerable importance for acceptable memory yields. Such vulnerabilities make it essential to investigate new robust design strategies at the circuit system level. In this paper we have analyzed the RRAM variability phenomenon, its impact and variation tolerant techniques at the circuit level. Finally a variation-monitoring circuit is presented that discerns the reliable memory cells affected by process variability.Peer ReviewedPostprint (author's final draft

Reliability analysis and micromechanics: A coupled approach for composite failure prediction

This work aims at associating two classical approaches for the design of composite materials: first, reliability methods that allow to account for the various uncertainties involved in the composite materials behaviour and lead to a rational estimation of their reliability level; on the other hand, micromechanics that derive macroscopic constitutive laws from micromechanical features. Such approach relies on the introduction of variabilities defined at the microscale and on the investigation of their consequences on the material macroscopic response through an homogenization scheme. Precisely, we propose here a systematic treatment of variability which involves a strong link between micro- and macroscales and provides a more exhaustive analysis of the influence of uncertainties. The paper intends to explain the main steps of such coupling and demonstrate its interests for material engineering, especially for constitutive modelling and composite materials optimization. An application case is developed throughout on the failure of unidirectional carbon fibre-reinforced composites with a comparative analysis between experimental data and simulation results

INFLUENCE OF MATERIAL CHARACTERIZATION IN THE DESIGN OF TUNNEL LIGHTING INSTALLATIONS

The paper describes the influence of the characterisation of reflectance behaviour of tunnel pavements and wall materials on the tunnel lighting design. CIE 189 document suggests considering lambertian behaviour for inter-reflection calculations for road luminance evaluation at design stage, because, unfortunately, no bi-directional reflection data for tunnel surfaces are commonly available. This simplification is supported by the low impact of inter- reflection contribution to road luminance. A European funded research project ha the task of developing the metrological support for the road surface characterisation in new geometries of measurements. The paper suggests to apply the outcomes on new geometries to tunnel wall materials characterisation suggesting that the suggested SURFACE observation angle of 2.29° can be useful for short tunnel too, including wall surfaces