Linear-logarithmic CMOS pixel with tunable dynamic range

Abstract—A CMOS pixel with linear–logarithmic response and programmable dynamic range (DR), based on a tunable transition point, has purposely been designed for endoscopic applications. A theoretical model of the pixel was developed and validated. A chip with a 100 × 100 pixel array and a 12-b digital output was fabricated in a 0.35-μm technology and was fully tested, thus demonstrating state-of-the-art performance in terms of DR and noise. Intraframe DR proved to be extendable to more than 110 dB through a logarithmic compression of the signal in the light ir-radiation power density (LIPD) range. The measured temporal noise (pixel noise) was less than 0.22 % over the full range. The architecture presented limited fixed pattern noise (FPN) due to the scheme adopted, which allowed its correction over the full signal range: FPN was 0.83 % (1.37%) in the linear (logarithmic) region. Although the test chip was designed mainly for endoscopic applications, the technology may also be applied to other fields, e.g., robotics, security and industrial automation, whenever high DR is a crucial feature. Index Terms—CMOS imager, endoscopy, logarithmic response, pixel. I

Low-power CMOS digital-pixel Imagers for high-speed uncooled PbSe IR applications

This PhD dissertation describes the research and development of a new low-cost medium wavelength infrared MWIR monolithic imager technology for high-speed uncooled industrial applications. It takes the baton on the latest technological advances in the field of vapour phase deposition (VPD) PbSe-based medium wavelength IR (MWIR) detection accomplished by the industrial partner NIT S.L., adding fundamental knowledge on the investigation of novel VLSI analog and mixed-signal design techniques at circuit and system levels for the development of the readout integrated device attached to the detector. The work supports on the hypothesis that, by the use of the preceding design techniques, current standard inexpensive CMOS technologies fulfill all operational requirements of the VPD PbSe detector in terms of connectivity, reliability, functionality and scalability to integrate the device. The resulting monolithic PbSe-CMOS camera must consume very low power, operate at kHz frequencies, exhibit good uniformity and fit the CMOS read-out active pixels in the compact pitch of the focal plane, all while addressing the particular characteristics of the MWIR detector: high dark-to-signal ratios, large input parasitic capacitance values and remarkable mismatching in PbSe integration. In order to achieve these demands, this thesis proposes null inter-pixel crosstalk vision sensor architectures based on a digital-only focal plane array (FPA) of configurable pixel sensors. Each digital pixel sensor (DPS) cell is equipped with fast communication modules, self-biasing, offset cancellation, analog-to-digital converter (ADC) and fixed pattern noise (FPN) correction. In-pixel power consumption is minimized by the use of comprehensive MOSFET subthreshold operation. The main aim is to potentiate the integration of PbSe-based infra-red (IR)-image sensing technologies so as to widen its use, not only in distinct scenarios, but also at different stages of PbSe-CMOS integration maturity. For this purpose, we posit to investigate a comprehensive set of functional blocks distributed in two parallel approaches: • Frame-based “Smart” MWIR imaging based on new DPS circuit topologies with gain and offset FPN correction capabilities. This research line exploits the detector pitch to offer fully-digital programmability at pixel level and complete functionality with input parasitic capacitance compensation and internal frame memory. • Frame-free “Compact”-pitch MWIR vision based on a novel DPS lossless analog integrator and configurable temporal difference, combined with asynchronous communication protocols inside the focal plane. This strategy is conceived to allow extensive pitch compaction and readout speed increase by the suppression of in-pixel digital filtering, and the use of dynamic bandwidth allocation in each pixel of the FPA. In order make the electrical validation of first prototypes independent of the expensive PbSe deposition processes at wafer level, investigation is extended as well to the development of affordable sensor emulation strategies and integrated test platforms specifically oriented to image read-out integrated circuits. DPS cells, imagers and test chips have been fabricated and characterized in standard 0.15μm 1P6M, 0.35μm 2P4M and 2.5μm 2P1M CMOS technologies, all as part of research projects with industrial partnership. The research has led to the first high-speed uncooled frame-based IR quantum imager monolithically fabricated in a standard VLSI CMOS technology, and has given rise to the Tachyon series [1], a new line of commercial IR cameras used in real-time industrial, environmental and transportation control systems. The frame-free architectures investigated in this work represent a firm step forward to push further pixel pitch and system bandwidth up to the limits imposed by the evolving PbSe detector in future generations of the device.La present tesi doctoral descriu la recerca i el desenvolupament d'una nova tecnologia monolítica d'imatgeria infraroja de longitud d'ona mitja (MWIR), no refrigerada i de baix cost, per a usos industrials d'alta velocitat. El treball pren el relleu dels últims avenços assolits pel soci industrial NIT S.L. en el camp dels detectors MWIR de PbSe depositats en fase vapor (VPD), afegint-hi coneixement fonamental en la investigació de noves tècniques de disseny de circuits VLSI analògics i mixtes pel desenvolupament del dispositiu integrat de lectura unit al detector pixelat. Es parteix de la hipòtesi que, mitjançant l'ús de les esmentades tècniques de disseny, les tecnologies CMOS estàndard satisfan tots els requeriments operacionals del detector VPD PbSe respecte a connectivitat, fiabilitat, funcionalitat i escalabilitat per integrar de forma econòmica el dispositiu. La càmera PbSe-CMOS resultant ha de consumir molt baixa potència, operar a freqüències de kHz, exhibir bona uniformitat, i encabir els píxels actius CMOS de lectura en el pitch compacte del pla focal de la imatge, tot atenent a les particulars característiques del detector: altes relacions de corrent d'obscuritat a senyal, elevats valors de capacitat paràsita a l'entrada i dispersions importants en el procés de fabricació. Amb la finalitat de complir amb els requisits previs, es proposen arquitectures de sensors de visió de molt baix acoblament interpíxel basades en l'ús d'una matriu de pla focal (FPA) de píxels actius exclusivament digitals. Cada píxel sensor digital (DPS) està equipat amb mòduls de comunicació d'alta velocitat, autopolarització, cancel·lació de l'offset, conversió analògica-digital (ADC) i correcció del soroll de patró fixe (FPN). El consum en cada cel·la es minimitza fent un ús exhaustiu del MOSFET operant en subllindar. L'objectiu últim és potenciar la integració de les tecnologies de sensat d'imatge infraroja (IR) basades en PbSe per expandir-ne el seu ús, no només a diferents escenaris, sinó també en diferents estadis de maduresa de la integració PbSe-CMOS. En aquest sentit, es proposa investigar un conjunt complet de blocs funcionals distribuïts en dos enfocs paral·lels: - Dispositius d'imatgeria MWIR "Smart" basats en frames utilitzant noves topologies de circuit DPS amb correcció de l'FPN en guany i offset. Aquesta línia de recerca exprimeix el pitch del detector per oferir una programabilitat completament digital a nivell de píxel i plena funcionalitat amb compensació de la capacitat paràsita d'entrada i memòria interna de fotograma. - Dispositius de visió MWIR "Compact"-pitch "frame-free" en base a un novedós esquema d'integració analògica en el DPS i diferenciació temporal configurable, combinats amb protocols de comunicació asíncrons dins del pla focal. Aquesta estratègia es concep per permetre una alta compactació del pitch i un increment de la velocitat de lectura, mitjançant la supressió del filtrat digital intern i l'assignació dinàmica de l'ample de banda a cada píxel de l'FPA. Per tal d'independitzar la validació elèctrica dels primers prototips respecte a costosos processos de deposició del PbSe sensor a nivell d'oblia, la recerca s'amplia també al desenvolupament de noves estratègies d'emulació del detector d'IR i plataformes de test integrades especialment orientades a circuits integrats de lectura d'imatge. Cel·les DPS, dispositius d'imatge i xips de test s'han fabricat i caracteritzat, respectivament, en tecnologies CMOS estàndard 0.15 micres 1P6M, 0.35 micres 2P4M i 2.5 micres 2P1M, tots dins el marc de projectes de recerca amb socis industrials. Aquest treball ha conduït a la fabricació del primer dispositiu quàntic d'imatgeria IR d'alta velocitat, no refrigerat, basat en frames, i monolíticament fabricat en tecnologia VLSI CMOS estàndard, i ha donat lloc a Tachyon, una nova línia de càmeres IR comercials emprades en sistemes de control industrial, mediambiental i de transport en temps real.Postprint (published version

Pixel and Readout Circuit of a Wide Dynamic Range Linear-Logarithmic Current-Mode Image Sensor

RESUME Le capteur d’images est la partie principale de tout système d’acquisition d’images, quelle que soit son application. Jusqu’à la fin des années 1990, les capteurs de type CCD ont dominé le marché en raison de leur qualité d’image exceptionnelle. À l’opposé des capteurs CCD, les capteurs CMOS offrent des possibilités intéressantes d’intégrer les circuits de traitement de signal sur un même substrat en vue d’obtenir une caméra sur puce. Entant que ces capteurs opèrent avec des tensions d’alimentations plus faibles que celles requise par les capteurs CCD, elles possèdent une faible consommation de puissance. De plus, les coûts associés à la fabrication des capteurs CMOS sont plus faibles que ceux engendrés par les capteurs CCD. Ces caractéristiques font en sorte que les capteurs d’images CMOS se prêtent à un plus grand nombre d’application que leurs équivalents CCD. Dans ce projet, l’objectif principal est de concevoir un capteur d’images ayant une plage dynamique élevée. Il possède l’avantage de deux modes d’opération, linéaire et logarithmique, ainsi qu’une lecture en mode courant afin d’augmenter sa plage dynamique. Les tensions d’alimentation des technologies CMOS diminue de plus en plus, et de ce fait la plage dynamique du pixel. En fonctionnant en mode courant, on arrive à atténuer cet effet. Le projet consiste à concevoir des circuits : convoyeur de courant, ‘delta-reset-sampling’ et un comparateur de courant qui sont efficaces pour les modes d’opération linéaire et logarithmique du pixel et permettent de détecter dans quels des deux modes se situe le pixel de façon à réaliser, à l’étage subséquent, une conversion analogique-numérique adéquate. Le pixel à trois transistors fonctionnant en mode courant utilise un transistor PMOS dans la région linéaire pour la lecture et un transistor PMOS de reset qui permet une réponse linéaire-logarithmique combinée. L'une des contributions à la non-linéarité de la réponse provient de l'effet provoqué par la résistance ‘on’ du transistor ‘select’. Pour éliminer cet effet, nous appliquons une fonction de linéarisation qui est effectuée dans le domaine numérique. Le mode d’opération du pixel est déterminé dans le circuit de lecture de colonne et un signal est envoyé à l'unité de traitement numérique comme indicateur de mode. Un prototype a été conçu et fabriqué en CMOS 0.35µm standard, 3.3V. Les résultats expérimentaux sont concluants et montrent une plage dynamique intrascènede 100 dB.----------ABSTRACT Digital cameras are rapidly becoming a dominant image capture devices. They are enabling many new applications. Charge-coupled devices (CCDs) have been the basis for solid state imaging since the 1970s. However, during the last decade, interest in CMOS imagers has increased significantly since they are capable of offering System-on-Chip (SoC) functionality. This can greatly reduce camera cost, power consumption, and size. Furthermore, by integrating innovative circuits on the same chip, the performance of CMOS image sensors could be extended beyond the capabilities of CCDs. Dynamic range is an important performance criterion for all image sensors. This thesis presents a current-mode CMOS image sensor operating in linear-logarithmic response. The objective of this design is to improve the dynamic range of the image sensor, and to provide a method for mode detection of the image sensor response. One of the motivations of using current-mode has been the shrinking feature size of CMOS devices. This leads to the reduction of supply voltage which causes the degradation of circuit performance in term of dynamic range. Such problem can be alleviated by operating in current-mode. The column readout circuits are designed in current-mode in order to be compatible with the image sensor. The readout circuit is composed of a first-generation current conveyor, an improved current memory is employed as a delta reset sampling unit, a differential amplifier as an integrator and a dynamic comparator. The current-mode three-transistor active pixel sensor uses a PMOS readout transistor in the linear region of operation and a PMOS reset transistor that allows for a linear-logarithmic response. One of the non-linearity contributions is the effect caused by the ‘on’ resistance of the select transistor. To eliminate this effect, we apply a linearization function that can be performed in the digital domain. The pixel response operation is determined in the column readout circuit and a signal is sent to the digital processing unit as an indicator. These circuits were implemented using a standard CMOS technology with no process modification. A prototype has been designed and fabricated in a standard AMS 2P4M, 3.3V, CMOS 0.35μm process from Austrian Microsystem

Matrix Transform Imager Architecture for On-Chip Low-Power Image Processing

Camera-on-a-chip systems have tried to include carefully chosen signal processing units for better functionality, performance and also to broaden the applications they can be used for. Image processing sensors have been possible due advances in CMOS active pixel sensors (APS) and neuromorphic focal plane imagers. Some of the advantages of these systems are compact size, high speed and parallelism, low power dissipation, and dense system integration. One can envision using these chips for portable and inexpensive video cameras on hand-held devices like personal digital assistants (PDA) or cell-phones In neuromorphic modeling of the retina it would be very nice to have processing capabilities at the focal plane while retaining the density of typical APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our MAtrix Transform Imager Architecture (MATIA) that uses analog floating--gate devices to make it possible to have computational imagers with high pixel densities. The core imager performs computations at the pixel plane, but still has a fill-factor of 46 percent - comparable to the high fill-factors of APS imagers. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image. The resulting data-flow architecture can directly perform all kinds of block matrix image transforms. Since the imager operates in the subthreshold region and thus has low power consumption, this architecture can be used as a low-power front end for any system that utilizes these computations. Various compression algorithms (e.g. JPEG), that use block matrix transforms, can be implemented using this architecture. Since MATIA can be used for gradient computations, cheap image tracking devices can be implemented using this architecture. Other applications of this architecture can range from stand-alone universal transform imager systems to systems that can compute stereoscopic depth.Ph.D.Committee Chair: Hasler, Paul; Committee Member: David Anderson; Committee Member: DeWeerth, Steve; Committee Member: Jackson, Joel; Committee Member: Smith, Mar

MOSFET Modulated Dual Conversion Gain CMOS Image Sensors

In recent years, vision systems based on CMOS image sensors have acquired significant ground over those based on charge-coupled devices (CCD). The main advantages of CMOS image sensors are their high level of integration, random accessibility, and low-voltage, low-power operation. Previously proposed high dynamic range enhancement schemes focused mainly on extending the sensor dynamic range at the high illumination end. Sensor dynamic range extension at the low illumination end has not been addressed. Since most applications require low-noise, high-sensitivity, characteristics for imaging of the dark region as well as dynamic range expansion to the bright region, the availability of a low-noise, high-sensitivity pixel device is particularly important. In this dissertation, a dual-conversion-gain (DCG) pixel architecture was proposed; this architecture increases the signal to noise ratio (SNR) and the dynamic range of CMOS image sensors at both the low and high illumination ends. The dual conversion gain pixel improves the dynamic range by changing the conversion gain based on the illumination level without increasing artifacts or increasing the imaging readout noise floor. A MOSFET is used to modulate the capacitance of the charge sensing node. Under high light illumination conditions, a low conversion gain is used to achieve higher full well capacity and wider dynamic range. Under low light conditions, a high conversion gain is enabled to lower the readout noise and achieve excellent low light performance. A sensor prototype using the new pixel architecture with 5.6μm pixel pitch was designed and fabricated using Micron Technology’s 130nm 3-metal and 2-poly silicon process. The periphery circuitries were designed to readout the pixel and support the pixel characterization needs. The pixel design, readout timing, and operation voltage were optimized. A detail sensor characterization was performed; a 127μV/e was achieved for the high conversion gain mode and 30.8μV/e for the low conversion gain mode. Characterization results confirm that a 42ke linear full well was achieved for the low conversion gain mode and 10.5ke for the high conversion gain mode. An average 2.1e readout noise was measured for the high conversion gain mode and 8.6e for the low conversion gain mode. The total sensor dynamic range was extended to 86dB by combining the two modes of operation with a 46.2dB maximum SNR. Several images were taken by the prototype sensor under different illumination levels. The simple processed color images show the clear advantage of the high conversion gain mode for the low light imaging