Crosstalk in SiC power MOSFETs for evaluation of threshold voltage shift caused by bias temperature instability

Threshold voltage drift from Bias Temperature Instability is known to be a reliability concern for SiC MOSFETs. Negative bias temperature instability (NBTI) results from positive charge trapping at the gate dielectric interface and is more problematic in SiC due to the higher interface trap density. Turning SiC MOSFETs OFF with negative voltages to avoid Miller coupling induced cross-talk can cause VTH shifts in periods with long standby duration and high temperatures. This paper proposes a novel test method for BTI characterization that relies on measuring the shoot-through current and charge during switching transients. The method exploits the Miller coupling between 2 devices in the same phase and uses the shoot-through current from parasitic turn-ON to monitor VTH. Standard techniques require the use of static measurements (typically from a parameter analyzer or a curve tracer) to determine the threshold voltage shift. These conventional methods can underestimate the VTH shift since the recovery from charge de-trapping can mask the true extent of the problem. The proposed methodology uses the actual converter environment to investigate the VTH shift and should therefore be of more interest to applications engineers as opposed to device physicists. Furthermore, it avoids the problem of VTH recovery and is therefore more accurate in VTH shift characterization

A novel non-intrusive technique for BTI characterization in SiC MOSFETs

Threshold voltage ( $V_{TH}$ ) shift due to Bias Temperature Instability (BTI) is a well-known problem in SiC-MOSFETs that occurs due to oxide traps in the $SiC/SiO_2$ gate interface. The reduced band offsets and increased interface/fixed oxide traps in SiC-MOSFETs makes this a more critical problem compared to silicon. Before qualification, power devices are subjected to gate bias stress tests after which $V_{TH}$ shift is monitored. However, some recovery occurs between the end of the stress and $V_{TH}$ characterisation, thereby potentially under-estimating the extent of the problem. In applications where the SiC-MOSFET is turned OFF with a negative bias at high temperature, if $V_{TH}$ shift is severe enough there may be electrothermal failure due to current crowding since parallel devices lose synchronization during turn-ON. In this paper, a novel method that uses the forward voltage of the body diode during reverse conduction of a small sensing current is introduced as a technique for monitoring $V_{TH}$ shift and recovery due to BTI. This non-invasive method exploits the increased body effect that is peculiar SiC-MOSFETs due to the higher body diode forward voltage. With the proposed method, it is possible to non-invasively assess $V_{TH}$ shift dynamically during BTI characterization tests

Non-intrusive methodologies for characterization of bias temperature instability in SiC power MOSFETs

The gate oxide reliability of SiC power MOSFETs remains a challenge, despite the improvements of the new generation power devices. The threshold voltage drift caused by Bias Temperature Instability (BTI) has been subject of different studies and methods have been proposed to evaluate the real magnitude of the threshold voltage shift. These methodologies usually focus on the characterization of the threshold voltage shift, rather than its implications to the operation or how the threshold voltage shift can be detected during the application. This paper presents two non-intrusive methodologies which can assess and determine the impact of BTI-induced. The proposed methodologies are able to capture the peak shift and subsequent recovery after stress removal

Impact of the gate oxide reliability of SiC MOSFETs on the junction temperature estimation using temperature sensitive electrical parameters

Bias temperature instability (BTI) is more problematic in SiC power MOSFETs due to the occurrence of higher interface state traps and fixed oxide traps compared to traditional silicon MOS interfaces where there are no carbon atoms degrading the atomically smooth Si/SiO2 interface. The use of temperature sensitive electrical parameters (TSEPs) for measuring the junction temperature and enabling health monitoring based on junction temperature identification is a promising technique for increasing the reliability of power devices, however in the light of increased BTI in SiC devices, this must be carefully assessed. This paper evaluates how BTI of SiC power MOSFETs under high temperature gate bias stresses affects the electrical parameters used as TSEPs and its impact on condition monitoring

Bias temperature instability and condition monitoring in SiC power MOSFETs

Threshold voltage shift due to bias temperature instability (BTI) is a major concern in SiC power MOSFETs. The SiC/SiO2 gate dielectric interface is typically characterized by a higher density of interface traps compared to the conventional Si/SiO2 interface. The threshold voltage shift that arises from BTI has significant implications on the reliability of SiC power MOSFETs, hence, techniques for detecting the change in electrical parameters due to gate oxide degradation are desirable. Using accelerated high temperature gate bias stress tests on SiC MOSFETs, it has been shown that the output and transfer characteristics are affected by BTI. This paper presents the impact BTI induced threshold voltage shift on the forward voltage of the SiC MOSFET body diode during third quadrant operation. Using the forward voltage of the body diode during reverse conduction of low currents, threshold voltage shift can be detected, hence, the impact of BTI can be evaluated. The implications of the body diode forward voltage shift on junction temperature measurements are also studied in the context of TSEPs. The findings in this paper are important for engineers seeking to implement condition and health monitoring techniques on SiC power devices

Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

Performance of Parallel Connected SiC MOSFETs under Short Circuits Conditions

This paper investigates the impact of parameter variation between parallel connected SiC MOSFETs on short circuit (SC) performance. SC tests are performed on parallel connected devices with different switching rates, junction temperatures and threshold voltages (VTH). The results show that VTH variation is the most critical factor affecting reduced robustness of parallel devices under SC. The SC current conducted per device is shown to increase under parallel connection compared to single device measurements. VTH shift from bias–temperature–instability (BTI) is known to occur in SiC MOSFETs, hence this paper combines BTI and SC tests. The results show that a positive VGS stress on the gate before the SC measurement reduces the peak SC current by a magnitude that is proportional to VGS stress time. Repeating the measurements at elevated temperatures reduces the time dependency of the VTH shift, thereby indicating thermal acceleration of negative charge trapping. VTH recovery is also observed using SC measurements. Similar measurements are performed on Si IGBTs with no observable impact of VGS stress on SC measurements. In conclusion, a test methodology for investigating the impact of BTI on SC characteristics is presented along with key results showing the electrothermal dynamics of parallel devices under SC conditions

Impact of BTI induced threshold voltage shifts in shoot-through currents from crosstalk in SiC MOSFETs

In this paper a method for evaluating the implications of threshold voltage (VTH) drift from gate voltage stress in SiC MOSFETs is presented. By exploiting the Miller coupling between two devices in the same phase leg, the technique uses the shoot-through charge from parasitic turn-ON to characterize the impact of Bias Temperature Instability (BTI) induced VTH shift. Traditional methods of BTI characterization rely on the application of a stress voltage without characterizing the implication of the VTH shift on the switching characteristics of the device in a circuit. Unlike conventional methods, this method uses the actual converter environment to investigate the implications of VTH shift and should therefore be of more interest to applications engineers as opposed to device physicists. Furthermore, a common problem is the underestimation of the VTH shift since recovery from charge de-trapping can mask the true extent of the problem. The impact of temperature, the recovery time after stress removal and polarity of the stress have been studied for a set of commercially available SiC MOSFETs

Trade-offs between gate oxide protection and performance in SiC MOSFETs

The reliability of gate oxides in SiC MOSFETs has come under increased scrutiny due to reduced performance under time dependent dielectric breakdown and increased threshold voltage instability. This paper investigates how 10% gate voltage (V GS ) derating in SiC MOSFETs can be implemented with minimal impact on loss performance. Using experimental measurements and electrothermal simulations of power converters, the trade-off between reduced V GS and conversion loss is investigated. It is shown that 10% V GS de-rating increases the ON-state resistance by 10% and the turn-ON switching energy by 7% average while the turn-OFF switching energy is unaffected. The low temperature sensitivity of the ON-state losses in SiC MOSFETs can be exploited since the rise in junction temperature due to V GS derating is marginal, unlike Si devices where ON-state resistance rises significantly with temperature. The load current and switching frequency influences the effectiveness of V GS derating. It is also shown that reducing the gate drive output impedance can compensate for V GS derating at high switching frequencies, with reduced total loss penalization. This may be important for protecting the gate oxide and enhancing its reliability