On the Complexity of the General Channel Routing Problem in the Knock-Knee Mode

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / 84-06-04

Switchbox Routing in VLSI Design: Closing the Complexity Gap

The design of integrated circuits has achieved a great deal of attention in the last decade. In the routing phase, there have survived two open layout problems which are important from both the theoretical and the practical point of view. Up to now, switchbox routing has been known to be solvable in polynomial time when there are only 2-terminal nets, and to be NP}-complete in case there exist nets involving at least five terminals. Our main result is that this problem is NP}-complete even if no net has more that three terminals. Hence, from the theoretical perspective, the SRP is completely settled. The NP–completeness proof is based on a reduction from a special kind of the satisfiability problem. It is also possible to adopt our construction to channel routing which shows that this problem is NP–complete, even if each net does not consist of more than five terminals. This improves upon a result of Sarrafzadeh who proved the NP–completeness in case of nets with no more than six terminals

An Elementary Theory of Layout Wirability

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / SRC RSCH 84-06-04

Routing through a generalized switchbox

We present an algorithm for the routing problem for two-terminal nets in generalized switchboxes. A generalized switchbox is any subset R of the planar rectangular grid with no non-trivial holes, i.e. every finite face has exactly four incident vertices. A net is a pair of nodes of non-maximal degree on the boundary of R. A solution is a set of edge-disjoint paths, one for each net. Our algorithm solves standard generalized switchbox routing problems in time O(n(log n)^2) where n is the number of vertices of R, i.e. it either finds a solution or indicates that there is none. A problem is standard if deg(v) + ter(v) is even for all vertices v where deg(v) is the degree of v and ter(v) is the number of nets which have v as a terminal. For nonstandard problems we can find a solution in time O(n(log n)^2 + |U|^2) where U is the set of vertices v with deg(v) + ter(v) is odd

A New Methodology for VLSI Layout

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / RSCH 84-06-049-

A Heuristic for Manhattan Routing

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / RSCH 83-01-03

A Density-Based General Greedy Channel Routing Algorithm in VLSI Design Automation.

One of the most important forms of routing strategies is called channel routing . This approach allows us to reduce the extremely difficult VLSI layout problem to a collection of simpler subproblems. For channel routing problems, most frequently mentioned heuristic algorithms use parameters derived from experiments to approach the routing solution without carefully considering the effect of each selected wire segment to the final routing solution. In this dissertation, we propose a new channel routing algorithm in the two-layer restricted-Manhattan routing model (2-RM) in detail. There are three phases involved in developing the new routing algorithm. In the first phase, we distinguish one type of wire from the others using some optimality criteria, which makes the selection of a set of best horizontal wire segments for a track more effective so that good performance of the generated routing solutions can be achieved. In the second phase, we develop a theoretical framework related to two major data structures, column density and vertical constraint graph, which effectively improves search efficiency and routing performance. Finally in the third phase, we develop an efficient powerful heuristic channel routing algorithm based on the concepts shown in phase one and the theoretical framework proposed in phase two. We highlight the application of our algorithm to the channel routing problems in the three-layer restricted-Manhattan overlap (3-RM-O) and three-layer Manhattan overlay (3-M-O) routing models. On many tests we have conducted on the examples known in the literature, our algorithm has performed as well or better than the existing algorithms in both 2-RM and 3-M-O routing models. Our experiments show that our approach has the potential to outperform other algorithms in other routing models

The Use of Parallel Processing in VLSI Computer-Aided Design Application

Coordinated Science Laboratory was formerly known as Control Systems LaboratorySemiconductor Research Corporation / 87-DP-10