166 research outputs found
A New Optimization Cost Model for VLSI Standard Cell Placement
In this paper, we propose a new optimization cost model for VLSI placement. It distinguishes itself from the traditional wire-length cost model by having direct impact on the quality of the detailed routing phase. We also extend the well-known simulated annealing standard cell placement algorithm by applying our new cost model. Experimental results show that we got 13% layout area reduction compared to traditional wire length model, 11% reduction to commercial tool.published_or_final_versio
A complete design path for the layout of flexible macros
XIV+172hlm.;24c
A Multiple-objective ILP based Global Routing Approach for VLSI ASIC Design
A VLSI chip can today contain hundreds of millions transistors and is expected to
contain more than 1 billion transistors in the next decade.
In order to handle this rapid growth in integration technology,
the design procedure is therefore divided into a sequence of design
steps. Circuit layout is the design step in which a physical
realization of a circuit is obtained from its functional description.
Global routing is one of the key subproblems of the circuit layout
which involves finding an approximate path for the wires connecting the
elements of the circuit without violating resource constraints.
The global routing problem is NP-hard, therefore, heuristics capable of
producing high quality routes with little computational effort are required
as we move into the Deep Sub-Micron (DSM) regime.
In this thesis, different approaches for global routing problem are first
reviewed. The advantages and disadvantages of these approaches are also summarized.
According to this literature review, several mathematical programming based global
routing models are fully investigated. Quality of solution obtained by
these models are then compared with traditional Maze routing technique.
The experimental results show that the proposed model can optimize several global routing
objectives simultaneously and effectively. Also, it is easy to incorporate new
objectives into the proposed global routing model.
To speedup the computation time of the proposed ILP based global router, several
hierarchical methods are combined with the flat ILP based global routing
approach. The experimental results indicate that the bottom-up global routing
method can reduce the computation time effectively with a slight increase of maximum
routing density.
In addition to wire area, routability, and vias, performance and low power
are also important goals in global routing, especially in deep submicron designs.
Previous efforts that focused on power optimization for global routing
are hindered by excessively long run times or the routing of a subset of the
nets. Accordingly, a power efficient multi-pin global routing
technique (PIRT) is proposed in this thesis.
This integer linear programming based techniques strives to find a power
efficient global routing solution.
The results indicate that an average power savings as high as 32\% for the
130-nm technology can be achieved with no impact on the maximum chip frequency
Intra Region Routing
The custom integrated circuit routing problem normally requires partitioning into rectangular routing regions. Natural partitions usually result in regions that form both channels and areas . This dissertation introduces several new channel and area routing algorithms and measures their performance.
A formal description of the channel routing problem is presented and a relationship is established between the selection of intervals for each track and the number of tracks in the completed channel. This relationship is used as an analysis tool that leads to the development of two new and highly effective channel routing algorithms: the Revised and LCP algorithms. The performance of these algorithms is compared against the Dogleg, Greedy, and several area routing algorithms over sets of randomly generated channels. The results indicate performance increases ranging from 2.74 to 34 times, depending on the characteristics of the channel.
In area routing, a new Degree of Freedom (DOF) based algorithm is developed that is straightforward to implement, is extensible to multipoint nets and reports if a path does not exist to complete the net. The quality of area routing algorithms is measured by the difficulty of the areas that can be successfully routed over sets of randomly generated areas. An extended definition of Manhattan Area Measure (MAM) is introduced as a measure of the difficulty of completing the wiring for areas with multipoint nets.
The results show that the DOF algorithm has higher completion rates than the Lee algorithm. This difference is greatest in areas with high aspect ratios. A new measure of the difficulty of an area is developed that places upper bounds on the performance of area routing algorithms. In areas with low aspect ratios, the drop in algorithm completion rates is closely related to this upper bound
A global routing technique for wave-steered design methodology
Wave-Steering is a new circuit design methodology to realize high throughput circuits by embedding layout friendly structures in silicon. Latches guarantee correct signal arrival times at the input of synthesized modules and maintain the high throughput of operation. This paper presents a global routing technique for networks of wave-steered blocks. Latches can be distributed along interconnects. Their number depends on net topologies and signal ordering at the inputs of wave steered blocks. here, we route nets using Steiner tree heuristics and determine signal ordering and latch positions on interconnect. The problem of total latch number minimization is solved using SAT formulation. Experimental results on benchmark circuits show the efficiency of our technique. We achieve on average a 40% latch reduction at minimum latency over un-optimized circuits operating at 250 MHz in 0.25 μm CMOS technology</p
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