Monitoring and Fault Location Sensor Network for Underground Distribution Lines

One of the fundamental tasks of electric distribution utilities is guaranteeing a continuous supply of electricity to their customers. The primary distribution network is a critical part of these facilities because a fault in it could affect thousands of customers. However, the complexity of this network has been increased with the irruption of distributed generation, typical in a Smart Grid and which has significantly complicated some of the analyses, making it impossible to apply traditional techniques. This problem is intensified in underground lines where access is limited. As a possible solution, this paper proposes to make a deployment of a distributed sensor network along the power lines. This network proposes taking advantage of its distributed character to support new approaches of these analyses. In this sense, this paper describes the aquiculture of the proposed network (adapted to the power grid) based on nodes that use power line communication and energy harvesting techniques. In this sense, it also describes the implementation of a real prototype that has been used in some experiments to validate this technological adaptation. Additionally, beyond a simple use for monitoring, this paper also proposes the use of this approach to solve two typical distribution system operator problems, such as: fault location and failure forecasting in power cables.Ministerio de Economía y Competitividad, Government of Spain project Sistema Inteligente Inalámbrico para Análisis y Monitorización de Líneas de Tensión Subterráneas en Smart Grids (SIIAM) TEC2013-40767-RMinisterio de Educación, Cultura y Deporte, Government of Spain, for the funding of the scholarship Formación de Profesorado Universitario 2016 (FPU 2016

Modeling and visualizing networked multi-core embedded software energy consumption

In this report we present a network-level multi-core energy model and a software development process workflow that allows software developers to estimate the energy consumption of multi-core embedded programs. This work focuses on a high performance, cache-less and timing predictable embedded processor architecture, XS1. Prior modelling work is improved to increase accuracy, then extended to be parametric with respect to voltage and frequency scaling (VFS) and then integrated into a larger scale model of a network of interconnected cores. The modelling is supported by enhancements to an open source instruction set simulator to provide the first network timing aware simulations of the target architecture. Simulation based modelling techniques are combined with methods of results presentation to demonstrate how such work can be integrated into a software developer's workflow, enabling the developer to make informed, energy aware coding decisions. A set of single-, multi-threaded and multi-core benchmarks are used to exercise and evaluate the models and provide use case examples for how results can be presented and interpreted. The models all yield accuracy within an average +/-5 % error margin

A new coupling solution for G3-PLC employment in MV smart grids

This paper proposes a new coupling solution for transmitting narrowband multicarrier power line communication (PLC) signals over medium voltage (MV) power lines. The proposed system is based on an innovative PLC coupling principle, patented by the authors, which exploits the capacitive divider embedded in voltage detecting systems (VDS) already installed inside the MV switchboard. Thus, no dedicated couplers have to be installed and no switchboard modifications or energy interruptions are needed. This allows a significant cost reduction of MV PLC implementation. A first prototype of the proposed coupling system was presented in previous papers: it had a 15 kHz bandwidth useful to couple single carrier PSK modulated PLC signals with a center frequency from 50–200 kHz. In this paper, a new prototype is developed with a larger bandwidth, up to 164 kHz, thus allowing to couple multicarrier G3-PLC signals using orthogonal frequency division multiplexing (OFDM) digital modulation. This modulation ensures a more robust communication even in harsh power line channels. In the paper, the new coupling system design is described in detail. A new procedure is presented for tuning the coupling system parameters at first installation in a generic MV switchboard. Finally, laboratory and in-field experimental test results are reported and discussed. The coupling performances are evaluated measuring the throughput and success rate in the case of both 18 and 36 subcarriers, in one of the different tone masks standardized for the FCC-above CENELEC band (that is, from 154.6875–487.5 kHz). The experimental results show an efficient behavior of the proposed coupler allowing a two-way communication of G3-PLC OFDM signals on MV networks

Overview of Swallow --- A Scalable 480-core System for Investigating the Performance and Energy Efficiency of Many-core Applications and Operating Systems

We present Swallow, a scalable many-core architecture, with a current configuration of 480 x 32-bit processors. Swallow is an open-source architecture, designed from the ground up to deliver scalable increases in usable computational power to allow experimentation with many-core applications and the operating systems that support them. Scalability is enabled by the creation of a tile-able system with a low-latency interconnect, featuring an attractive communication-to-computation ratio and the use of a distributed memory configuration. We analyse the energy and computational and communication performances of Swallow. The system provides 240GIPS with each core consuming 71--193mW, dependent on workload. Power consumption per instruction is lower than almost all systems of comparable scale. We also show how the use of a distributed operating system (nOS) allows the easy creation of scalable software to exploit Swallow's potential. Finally, we show two use case studies: modelling neurons and the overlay of shared memory on a distributed memory system.Comment: An open source release of the Swallow system design and code will follow and references to these will be added at a later dat

Enhanced secure key exchange systems based on the Johnson-noise scheme

We introduce seven new versions of the Kirchhoff-Law-Johnson-(like)-Noise (KLJN) classical physical secure key exchange scheme and a new transient protocol for practically-perfect security. While these practical improvements offer progressively enhanced security and/or speed for the non-ideal conditions, the fundamental physical laws providing the security remain the same. In the "intelligent" KLJN (iKLJN) scheme, Alice and Bob utilize the fact that they exactly know not only their own resistor value but also the stochastic time function of their own noise, which they generate before feeding it into the loop. In the "multiple" KLJN (MKLJN) system, Alice and Bob have publicly known identical sets of different resistors with a proper, publicly known truth table about the bit-interpretation of their combination. In the "keyed" KLJN (KKLJN) system, by using secure communication with a formerly shared key, Alice and Bob share a proper time-dependent truth table for the bit-interpretation of the resistor situation for each secure bit exchange step during generating the next key. The remaining four KLJN schemes are the combinations of the above protocols to synergically enhance the security properties. These are: the "intelligent-multiple" (iMKLJN), the "intelligent-keyed" (iKKLJN), the "keyed-multiple" (KMKLJN) and the "intelligent-keyed-multiple" (iKMKLJN) KLJN key exchange systems. Finally, we introduce a new transient-protocol offering practically-perfect security without privacy amplification, which is not needed at practical applications but it is shown for the sake of ongoing discussions.Comment: This version is accepted for publicatio

Development and implementation of a LabVIEW based SCADA system for a meshed multi-terminal VSC-HVDC grid scaled platform

This project is oriented to the development of a Supervisory, Control and Data Acquisition (SCADA) software to control and supervise electrical variables from a scaled platform that represents a meshed HVDC grid employing National Instruments hardware and LabVIEW logic environment. The objective is to obtain real time visualization of DC and AC electrical variables and a lossless data stream acquisition. The acquisition system hardware elements have been configured, tested and installed on the grid platform. The system is composed of three chassis, each inside of a VSC terminal cabinet, with integrated Field-Programmable Gate Arrays (FPGAs), one of them connected via PCI bus to a local processor and the rest too via Ethernet through a switch. Analogical acquisition modules were A/D conversion takes place are inserted into the chassis. A personal computer is used as host, screen terminal and storing space. There are two main access modes to the FPGAs through the real time system. It has been implemented a Scan mode VI to monitor all the grid DC signals and a faster FPGA access mode VI to monitor one converter AC and DC values. The FPGA application consists of two tasks running at different rates and a FIFO has been implemented to communicate between them without data loss. Multiple structures have been tested on the grid platform and evaluated, ensuring the compliance of previously established specifications, such as sampling and scanning rate, screen refreshment or possible data loss. Additionally a turbine emulator was implemented and tested in Labview for further testing

Current and voltage based bit errors and their combined mitigation for the Kirchhoff-law-Johnson-noise secure key exchange

We classify and analyze bit errors in the current measurement mode of the Kirchhoff-law-Johnson-noise (KLJN) key distribution. The error probability decays exponentially with increasing bit exchange period and fixed bandwidth, which is similar to the error probability decay in the voltage measurement mode. We also analyze the combination of voltage and current modes for error removal. In this combination method, the error probability is still an exponential function that decays with the duration of the bit exchange period, but it has superior fidelity to the former schemes.Comment: 9 pages, accepted for publication in Journal of Computational Electronic