3,418 research outputs found

    ToPoliNano: Nanoarchitectures Design Made Real

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    Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing. We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits. ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologie

    Magnetic cooling for microkelvin nanoelectronics on a cryofree platform

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    We present a parallel network of 16 demagnetization refrigerators mounted on a cryofree dilution refrigerator aimed to cool nanoelectronic devices to sub-millikelvin temperatures. To measure the refrigerator temperature, the thermal motion of electrons in a Ag wire -- thermalized by a spot-weld to one of the Cu nuclear refrigerators -- is inductively picked-up by a superconducting gradiometer and amplified by a SQUID mounted at 4 K. The noise thermometer as well as other thermometers are used to characterize the performance of the system, finding magnetic field independent heat-leaks of a few nW/mol, cold times of several days below 1 mK, and a lowest temperature of 150 microK of one of the nuclear stages in a final field of 80 mT, close to the intrinsic SQUID noise of about 100 microK. A simple thermal model of the system capturing the nuclear refrigerator, heat leaks, as well as thermal and Korringa links describes the main features very well, including rather high refrigerator efficiencies typically above 80%.Comment: 4 color figures, including supplementary inf

    From Microelectronics to Nanoelectronics: Introducing Nanotechnology to VLSI Curricula

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    © 2011 by ASEEIn the past decades, VLSI industries constantly shrank the size of transistors, so that more and more transistors can be built into the same chip area to make VLSI more and more powerful in its functions. As the typical feature size of CMOS VLSI is shrunk into deep submicron domain, nanotechnology is the next step in order to maintain Moore’s law for several more decades. Nanotechnology not only further improves the resolution in traditional photolithography process, but also introduces many brand-new fabrication strategies, such as bottom-up molecular self-assembly. Nanotechnology is also enabling many novel devices and circuit architectures which are totally different from current microelectronics circuits, such as quantum computing, nanowire crossbar circuits, spin electronics, etc. Nanotechnology is bringing another technology revolution to traditional CMOS VLSI technology. In order to train students to meet the quickly-increasing industry demand for nextgeneration nanoelectronics engineers, we are making efforts to introduce nanotechnology into our VLSI curricula. We have developed a series of VLSI curricula which include CPE/EE 448D - Introduction to VLSI, EE 548 - Low Power VLSI Circuit Design, EE 458 - Analog VLSI Circuit Design, EE 549 - VLSI Testing, etc. Furthermore, we developed a series of micro and nanotechnology related courses, such as EE 451 - Nanotechnology, EE 448 - Microelectronic Fabrication, EE 446 – MEMS (Microelectromechanical Systems). We introduce nanotechnology into our VLSI curricula, and teach the students about various devices, fabrication processes, circuit architectures, design and simulation skills for future nanotechnology-based nanoelectronic circuits. Some examples are nanowire crossbar circuit architecture, carbon-nanotube based nanotransistor, single-electron transistor, spintronics, quantum computing, bioelectronic circuits, etc. Students show intense interest in these exciting topics. Some students also choose nanoelectronics as the topic for their master project/thesis, and perform successful research in the field. The program has attracted many graduate students into the field of nanoelectronics

    Highlights of today’s scientific research and its funding

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    On 18 December 2006, the Council adopted decisions establishing the Seventh Framework Programme of the European Community (EC) for research and technological development for the period 2007 to 2013, and the FP7 for nuclear research activities (Euratom) for 2007 to 2011. The Council also adopted a regulation laying down the rules for the participation of undertakings, research centres and universities in actions under FP7-EC and for the dissemination of research results. The programme places greater emphasis than in the past on research that is relevant to the needs of European industry, to help it compete internationally, and develop its role as a world leader in certain sectors. The programme will also for the first time provide support for the best in European investigator-driven research, with the creation of a European Research Council. Focus will be on excellence throughout the programme, a requirement if it is to play its role in developing Europe's global competitiveness. Another priority will be to make participation in the programme simpler and easier, through measures addressing the procedures, plus a rationalisation of instruments.knowledge based society; scientific research; dissemination of research results; excellence centres, global competitiveness

    Hierarchical Composition of Memristive Networks for Real-Time Computing

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    Advances in materials science have led to physical instantiations of self-assembled networks of memristive devices and demonstrations of their computational capability through reservoir computing. Reservoir computing is an approach that takes advantage of collective system dynamics for real-time computing. A dynamical system, called a reservoir, is excited with a time-varying signal and observations of its states are used to reconstruct a desired output signal. However, such a monolithic assembly limits the computational power due to signal interdependency and the resulting correlated readouts. Here, we introduce an approach that hierarchically composes a set of interconnected memristive networks into a larger reservoir. We use signal amplification and restoration to reduce reservoir state correlation, which improves the feature extraction from the input signals. Using the same number of output signals, such a hierarchical composition of heterogeneous small networks outperforms monolithic memristive networks by at least 20% on waveform generation tasks. On the NARMA-10 task, we reduce the error by up to a factor of 2 compared to homogeneous reservoirs with sigmoidal neurons, whereas single memristive networks are unable to produce the correct result. Hierarchical composition is key for solving more complex tasks with such novel nano-scale hardware

    Error-triggered Three-Factor Learning Dynamics for Crossbar Arrays

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    Recent breakthroughs suggest that local, approximate gradient descent learning is compatible with Spiking Neural Networks (SNNs). Although SNNs can be scalably implemented using neuromorphic VLSI, an architecture that can learn in-situ as accurately as conventional processors is still missing. Here, we propose a subthreshold circuit architecture designed through insights obtained from machine learning and computational neuroscience that could achieve such accuracy. Using a surrogate gradient learning framework, we derive local, error-triggered learning dynamics compatible with crossbar arrays and the temporal dynamics of SNNs. The derivation reveals that circuits used for inference and training dynamics can be shared, which simplifies the circuit and suppresses the effects of fabrication mismatch. We present SPICE simulations on XFAB 180nm process, as well as large-scale simulations of the spiking neural networks on event-based benchmarks, including a gesture recognition task. Our results show that the number of updates can be reduced hundred-fold compared to the standard rule while achieving performances that are on par with the state-of-the-art
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