STT-MRAM characterization and its test implications

Spin torque transfer (STT)-magnetoresistive random-access memory (MRAM) has come a long way in research to meet the speed and power consumption requirements for future memory applications. The state-of-the-art STT-MRAM bit-cells employ magnetic tunnel junction (MTJ) with perpendicular magnetic anisotropy (PMA). The process repeatabil- ity and yield stability for wafer fabrication are some of the critical issues encountered in STT-MRAM mass production. Some of the yield improvement techniques to combat the e ect of process variations have been previously explored. However, little research has been done on defect oriented testing of STT-MRAM arrays. In this thesis, the author investi- gates the parameter deviation and non-idealities encountered during the development of a novel MTJ stack con guration. The characterization result provides motivation for the development of the design for testability (DFT) scheme that can help test and characterize STT-MRAM bit-cells and the CMOS peripheral circuitry e ciently. The primary factors for wafer yield degradation are the device parameter variation and its non-uniformity across the wafer due to the fabrication process non-idealities. There- fore, e ective in-process testing strategies for exploring and verifying the impact of the parameter variation on the wafer yield will be needed to achieve fabrication process opti- mization. While yield depends on the CMOS process variability, quality of the deposited MTJ lm, and other process non-idealities, test platform can enable parametric optimiza- tion and veri cation using the CMOS-based DFT circuits. In this work, we develop a DFT algorithm and implement a DFT circuit for parametric testing and prequali cation of the critical circuits in the CMOS wafer. The DFT circuit successfully replicates the electrical characteristics of MTJ devices and captures their spatial variation across the wafer with an error of less than 4%. We estimate the yield of the read sensing path by implement- ing the DFT circuit, which can replicate the resistance-area product variation up to 50% from its nominal value. The yield data from the read sensing path at di erent wafer loca- tions are analyzed, and a usable wafer radius has been estimated. Our DFT scheme can provide quantitative feedback based on in-die measurement, enabling fabrication process optimization through iterative estimation and veri cation of the calibrated parameters. Another concern that prevents mass production of STT-MRAM arrays is the defect formation in MTJ devices due to aging. Identifying manufacturing defects in the magnetic tunnel junction (MTJ) device is crucial for the yield and reliability of spin-torque-transfer (STT) magnetic random-access memory (MRAM) arrays. Several of the MTJ defects result in parametric deviations of the device that deteriorate over time. We extend our work on the DFT scheme by monitoring the electrical parameter deviations occurring due to the defect formation over time. A programmable DFT scheme was implemented for a sub-arrayin 65 nm CMOS technology to evaluate the feasibility of the test scheme. The scheme utilizes the read sense path to compare the bit-cell electrical parameters against known DFT cells characteristics. Built-in-self-test (BIST) methodology is utilized to trigger the onset of the fault once the device parameter crosses a threshold value. We demonstrate the operation and evaluate the accuracy of detection with the proposed scheme. The DFT scheme can be exploited for monitoring aging defects, modeling their behavior and optimization of the fabrication process. DFT scheme could potentially nd numerous applications for parametric characteriza- tion and fault monitoring of STT-MRAM bit-cell arrays during mass production. Some of the applications include a) Fabrication process feedback to improve wafer turnaround time, b) STT-MRAM bit-cell health monitoring, c) Decoupled characterization of the CMOS pe- ripheral circuitry such as read-sensing path and sense ampli er characterization within the STT-MRAM array. Additionally, the DFT scheme has potential applications for detec- tion of fault formation that could be utilized for deploying redundancy schemes, providing a graceful degradation in MTJ-based bit-cell array due to aging of the device, and also providing feedback to improve the fabrication process and yield learning

Mechanism and assessment of spin transfer torque (STT) based memory

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 61-70).When a sufficient current density passes through the MTJ, the spin-polarized current will exert a spin transfer torque to switch the magnetization of the free layer. This is the fundamental of the novel write mechanism in STT-RAM, current-induced magnetization switching. It allows STT-RAM to have a smaller cell size and write current than MRAM, and also capable of what MRAM promises: fast, dense, and non-volatile. A technological assessment was conducted to verify the claims of STT-RAM by understanding the physical principles behind it. A comparison of performance parameters in various memory technologies was also made. STT-RAM scores well in all aspect except in the size of the memory cell. The high current density (>10⁶ A/cm²) sets the lower limit of the size of the driving transistor and ultimately the cost of manufacturing STT-RAM. Cost models were presented to estimate the cost of a STT-RAM based on a three mask levels fabrication process. Although much effort has been put into reducing the switching current density, there are still no easy solutions to the problem. Research and development of STT-RAM must show success in a very near future or else STT-RAM will follow the step of its predecessor, MRAM: surviving in the niche market.by Iong Ying Loh.M.Eng

Energy and Area Efficient Machine Learning Architectures using Spin-Based Neurons

Recently, spintronic devices with low energy barrier nanomagnets such as spin orbit torque-Magnetic Tunnel Junctions (SOT-MTJs) and embedded magnetoresistive random access memory (MRAM) devices are being leveraged as a natural building block to provide probabilistic sigmoidal activation functions for RBMs. In this dissertation research, we use the Probabilistic Inference Network Simulator (PIN-Sim) to realize a circuit-level implementation of deep belief networks (DBNs) using memristive crossbars as weighted connections and embedded MRAM-based neurons as activation functions. Herein, a probabilistic interpolation recoder (PIR) circuit is developed for DBNs with probabilistic spin logic (p-bit)-based neurons to interpolate the probabilistic output of the neurons in the last hidden layer which are representing different output classes. Moreover, the impact of reducing the Magnetic Tunnel Junction\u27s (MTJ\u27s) energy barrier is assessed and optimized for the resulting stochasticity present in the learning system. In p-bit based DBNs, different defects such as variation of the nanomagnet thickness can undermine functionality by decreasing the fluctuation speed of the p-bit realized using a nanomagnet. A method is developed and refined to control the fluctuation frequency of the output of a p-bit device by employing a feedback mechanism. The feedback can alleviate this process variation sensitivity of p-bit based DBNs. This compact and low complexity method which is presented by introducing the self-compensating circuit can alleviate the influences of process variation in fabrication and practical implementation. Furthermore, this research presents an innovative image recognition technique for MNIST dataset on the basis of p-bit-based DBNs and TSK rule-based fuzzy systems. The proposed DBN-fuzzy system is introduced to benefit from low energy and area consumption of p-bit-based DBNs and high accuracy of TSK rule-based fuzzy systems. This system initially recognizes the top results through the p-bit-based DBN and then, the fuzzy system is employed to attain the top-1 recognition results from the obtained top outputs. Simulation results exhibit that a DBN-Fuzzy neural network not only has lower energy and area consumption than bigger DBN topologies while also achieving higher accuracy

An analysis of MRAM based memory technologies

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2006.Includes bibliographical references (leaves 66-68).MRAM is a memory (RAM) technology that uses electron spin to store information. Often been called "the ideal memory", it can potentially combine the density of DRAM with the speed of SRAM and non-volatility of FLASH memory or hard disk, and all this while consuming a very low amount of power. However, it is the need for a fast and non-volatile computer memory that has been the key driver for evolution of this technology. At the moment, MRAM is in its final stages of development and much of the current research concentrates on issues like reducing the write current, increasing the density and making the process more reproducible. A lot of companies are pursuing research on this technology and are likely to introduce it into the market in the near future. However, it will be a while before MRAM can replace conventional memories. Nevertheless, since MRAM can resist high radiation, and can operate in extreme temperature conditions, it is likely that we will see the first MRAM in applications that need such properties.by Rangarajan Vijayaraghavan.M.Eng

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Electric field control of fixed magnetic Skyrmions for energy efficient nanomagnetic memory

To meet the ever-growing demand of faster and smaller computers, increasing number of transistors are needed in the same chip area. Unfortunately, Silicon based transistors have almost reached their miniaturization limits mainly due to excessive heat generation. Nanomagnetic devices are one of the most promising alternatives of CMOS. In nanomagnetic devices, electron spin, instead of charge, is the information carrier. Hence, these devices are non-volatile: information can be stored in these devices without needing any external power which could enable computing architectures beyond traditional von-Neumann computing. Additionally, these devices are also expected to be more energy efficient than CMOS devices as their operation does not involve translation of charge across the device. However, the energy dissipated in the clocking circuitry negates this perceived advantage and in practice CMOS devices still consume three orders of magnitudes less energy. Therefore, researchers have been looking for nanomagnetic devices that could be energy efficient in addition to being non-volatile which has led to the exploration of several switching strategies. Among those, electric field induced switching has proved to be a promising route towards scalable ultra-low power computing devices. Particularly Voltage Control of Magnetic Anisotropy (VCMA) based switching dissipates ~1 fJ energy. However, incoherence due to thermal noise and material inhomogeneity renders this switching error-prone. This dissertation is devoted towards studying VCMA induced switching of a spin spiral magnetic state, magnetic skyrmions, which can potentially alleviate this issue. Magnetic skyrmions has recently emerged as a viable candidate to be used in room temperature nanomagnetic devices. Most of the studies propose to utilize skyrmion motion in a magnetic track to implement memory devices. However, Magnetic Tunnel Junction (MTJ) devices based on skyrmions that are fixed in space might be advantageous in terms of footprint. To establish a new computing paradigm based on electrical manipulation of magnetization of fixed magnetic skyrmions we have studied: i) Purely VCMA induced reversal of magnetic skyrmions using extensive micromagnetic simulations. This shows sequential increase and decrease of Perpendicular Magnetic Anisotropy (PMA) can result into toggling between skyrmionic and ferromagnetic states. We also demonstrate VCMA assisted Spin Transfer Torque (STT) induced reversal of magnetic skyrmions. ii) Complete reversal of ferromagnets mediated by intermediated skyrmion state using rigorous micromagnetic simulation. We show that the switching can be robust by limiting the “phase space” of the magnetization dynamics through a controlled skyrmion state. Thus, the switching error can be lowered compared to conventional VCMA switching. iii) Finally, we perform preliminary experiments on VCMA induced manipulation of skyrmions. We demonstrate that skyrmions can be annihilated when Perpendicular Magnetic Anisotropy of the system is increased by applying a negative voltage pulse and can be recreated by decreasing PMA by applying a positive voltage pulse. The experimental observations are corroborated using micromagnetic simulation. Future research should focus on demonstrating reversal of skyrmions experimentally in MTJ like devices and study the downscaling of the proposed device. These can enable realization of energy efficient and robust nanomagnetic memory devices based on voltage control switching of fixed magnetic skyrmions as wells as other neuromorphic computing devices

Towards Oxide Electronics:a Roadmap

At the end of a rush lasting over half a century, in which CMOS technology has been experiencing a constant and breathtaking increase of device speed and density, Moore's law is approaching the insurmountable barrier given by the ultimate atomic nature of matter. A major challenge for 21st century scientists is finding novel strategies, concepts and materials for replacing silicon-based CMOS semiconductor technologies and guaranteeing a continued and steady technological progress in next decades. Among the materials classes candidate to contribute to this momentous challenge, oxide films and heterostructures are a particularly appealing hunting ground. The vastity, intended in pure chemical terms, of this class of compounds, the complexity of their correlated behaviour, and the wealth of functional properties they display, has already made these systems the subject of choice, worldwide, of a strongly networked, dynamic and interdisciplinary research community. Oxide science and technology has been the target of a wide four-year project, named Towards Oxide-Based Electronics (TO-BE), that has been recently running in Europe and has involved as participants several hundred scientists from 29 EU countries. In this review and perspective paper, published as a final deliverable of the TO-BE Action, the opportunities of oxides as future electronic materials for Information and Communication Technologies ICT and Energy are discussed. The paper is organized as a set of contributions, all selected and ordered as individual building blocks of a wider general scheme. After a brief preface by the editors and an introductory contribution, two sections follow. The first is mainly devoted to providing a perspective on the latest theoretical and experimental methods that are employed to investigate oxides and to produce oxide-based films, heterostructures and devices. In the second, all contributions are dedicated to different specific fields of applications of oxide thin films and heterostructures, in sectors as data storage and computing, optics and plasmonics, magnonics, energy conversion and harvesting, and power electronics

Treated HfO2 based rram devices with ru, tan, tin as top electrode for in-memory computing hardware

The scalability and power efficiency of the conventional CMOS technology is steadily coming to a halt due to increasing problems and challenges in fabrication technology. Many non-volatile memory devices have emerged recently to meet the scaling challenges. Memory devices such as RRAMs or ReRAM (Resistive Random-Access Memory) have proved to be a promising candidate for analog in memory computing applications related to inference and learning in artificial intelligence. A RRAM cell has a MIM (Metal insulator metal) structure that exhibits reversible resistive switching on application of positive or negative voltage. But detailed studies on the power consumption, repeatability and retention of during multi-level operation have not been undertaken previously. Transition metal oxide-based RRAMs, using HfO2, executes change in resistance (switching behavior) via electrochemical migration of oxygen vacancies. This thesis investigates the role of extra oxygen vacancies, introduced by plasma exposure (treated), in HfO2 to reduce the power consumption of RRAM. In addition to oxygen vacancy rich HfO2, various top metal electrodes including Ruthenium (Ru) are explored to enhance the switching behavior and power consumption. Use of Ru as a top metal reduced the switching energy of the treated HfO2 RRAM device