dRail: a novel physical layout methodology for power gated circuits

In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM Cortex-A5 processor using a 65nm library, and shows up to 38% reduction in area cost when compared to traditional voltage area layou

Ultra-Low Leakage, Energy-Efficient Digital Integrated Circuit and System Design

The advances of the complementary metal-oxide-semiconductor (CMOS) technology manufacturing and design over the years have enabled a diverse range of applications across the power consumption, performance, and area (PPA) spectra. Many of the recent and prospective applications rely on the availability of energy-autonomous, miniaturized systems, i.e., ultra-low power (ULP) VLSI systems, which are generally characterized by extreme resource limitations. Some examples of applications are wireless sensing platforms, body-area sensor networks (BASN), biomedical and implantable devices, wearables, hearables, and monitors. Within the context of such applications, the key requirements are long lifetime and miniaturized size (sub-/millimeter-scale). In order to enable both requirements, energy-efficiency is the key metric. It allows for extended battery lifetime and operation with the energy that can be harvested from the environment, and it limits the size (volume) of the energy sources utilized to power these systems. Ultra-low voltage (ULV) operation is a key technique in which the VDD of circuits is reduced from nominal to near or below the threshold voltage of the transistor. It is a powerful knob that has been largely exploited by designers in order to achieve ultra-low power consumption and high energy-efficiency in CMOS. Existing ULP VLSI systems typically operate at a lower supply voltage thereby reducing their energy consumption by one to two orders of magnitude in order to enable the aforementioned applications. While supply voltage scaling is a promising measure for achieving low power and reducing energy consumption, it brings up several challenges. One critical issue is the leakage energy dissipated by the devices, which is magnified in portion to the total energy consumption at ULV. The reason is that, as VDD scales from nominal to near-threshold and sub-threshold, transistors become increasingly slower and they accumulate more leakage (i.e., static) power over longer cycle times. This energy waste accounts for a significant portion of the system's total energy consumption, offsets the gains provided by voltage scaling, defines the minimum energy per operation, and poses a practical limit for the system's energy-efficiency. This thesis presents selected research works on ultra-low leakage, energy-efficient digital integrated circuit design. More specifically, it describes novel and key techniques for minimizing the energy waste of idle/underutilized and always-on hardware. The main goal of such techniques is to push the envelope of energy-efficiency in energy-autonomous, miniaturized VLSI systems. Such techniques are applied to key building blocks of emerging mobile and embedded computing devices resulting in state-of-the-art energy-efficiencies

Utilização de aritmética bit-serial para redução de consumo de energia.

Hoje, uma das maiores preocupações, senão a maior, da indústria de semicondutores é o desenvolvimento de chips com baixo consumo de energia. Existem vários fenômenos físicos causadores de consumo de energia em circuitos CMOS e várias técnicas que reduzem o consumo de energia de um chip. O objetivo principal desta pesquisa de mestrado foi investigar o quanto o consumo de energia estática em circuitos CMOS pode ser reduzido por meio do emprego de aritmética bit-serial em substituição à aritmética bit-paralela. A pesquisa está focada em circuitos construídos a partir de standard cells (células padrão), com aplicação em processamento de sinais, e para os quais o principal requisito não é o alto desempenho computacional, mas o baixo consumo de energia. A metodologia foi aplicada em um estudo de caso, utilizando-se para isto, simulações com o IP core SPVR. O SPVR é um verificador de identidade vocal implementado em um circuito dedicado capaz de ter desempenho suficiente para funcionar em tempo real, mesmo empregando um sinal de clock lento. Foi constatado na pesquisa, que o uso de aritmética bit-serial, em termos de diminuição de consumo estático, é vantajoso para somadores e circuitos de pequena complexidade. Porém, para sistemas de maior complexidade, esta substituição só é vantajosa em situações específicas de grande número de operações aritméticas e baixo uso de armazenamento em registradores paralelos. No caso inverso, as vantagens se perdem, porque embora haja diminuição de consumo estático, há um crescimento muito grande de consumo dinâmico.Today, one of the biggest concerns, if not the largest, for the semiconductor industry is the development of chips with low power consumption. There are several physical phenomena that cause power consumption in CMOS circuits and various techniques that reduce the energy consumption of a chip. The main objective of this masters research was to investigate how the static power consumption in CMOS circuits can be reduced through the use of bit-serial arithmetic in place of bit-parallel arithmetic. The research is focused on circuits built from standard cells, with application to signal processing, and for which the main requirement is not the high computing performance, but the low power consumption. The methodology was applied in a case study, using for this, simulations with the SPVR IP core. The SPVR is a vocal identity checker implemented in a dedicated circuit able to have enough performance to run in real time, even employing a slow clock signal. It has been found in research that the use of bit-serial arithmetic, in terms of reduction of static consumption, is advantageous to adders and small circuit complexity. However, for more complex systems, this substitution is only advantageous in specific situations of large number of arithmetic operations and low storage usage in parallel registers. In the reverse case, the advantages are lost, because although there are static consumption decrease, there is a very large dynamic consumption growth