High Speed Fully Monolihic Self-Triggered Dc-Dc Buck Converter

The integration of DC-DC converter in standard CMOS process faces challenges from the low transistor breakdown voltages, poor quality factor and large size on-chip capacitors and inductors. The standard solution to deal with the problem of MOS transistor’s low breakdown voltage is using cascode configuration in the output stage. High-side PMOS and low-side NMOS power transistors in on-chip buck converter are switched ON and OFF with non-overlapping driving signals whose duty- cycle regulate the output voltage of converter. The non-overlapping driving signals are required to avoid short-circuit losses through power transistors. By using the cascode configuration, driving signals for high-side PMOS and low-side NMOS power switching transistors operate in different voltage domains. To overcome this problem, the voltage level shifters are needed to transfer driving signals between two voltage domains. However, associated power losses and additional timing delays in conventional level shifters may deteriorate the overall efficiency of converter. In order to avoid the losses and timing delays associated with the level shifters, a self-triggered buck converter is proposed in this work. The high-side driving signal is generated from the converter output via inductive feedback. The inductive feedback eliminates the required level shifters needed for transferring the driving signal to highside power transistor. The inductive feedback has fast response and provides adaptive dead-time that avoids short circuit losses with no additional hardware. Output voltage regulation is realized by controlling the duty-cycle of the signal switching the low-side NMOS transistor. Simulations are done on Cadence 45nm CMOS General Process Design Kit(GPDK) and show that the efficiency of self-triggered converter (64.25%) is better than the efficiency of a hard-switching buck converter(63.21%), even when the level shifter losses and delays are not taken into account. The converter generate output voltage ~1.5V ± 20mV and average load current 100mA ± 3mA from 3V-3.6V input at a switching frequency of 360MHz. In order to closely match real circuit behavior, layout is made and final simulations are carried out with extracted layout and PCB Parasitics. The converter is fully integrated with 1.73×1.62[mm×mm] area on silicon including power stage, transformer, decoupling capacitors and pad

Design of compact frequency synthesizer for self-calibration in RF circuits

A compact frequency synthesizer based on a phase locked loop (PLL) is designed for the self-calibration in RF circuits. The main advantage of the presented frequency synthesizer is that it can be built in a small silicon area using MOSFET interface trap charge pump (ITCP) current generators. The ITCP current generator makes it possible to use small currents at nano-ampere levels so that small capacitances can be used in the loop filter. A large resistance, which is required to compensate for the reduced capacitances, is implemented using an operational transconductance amplifier (OTA). An ITCP current generator is used as a tail current source for the OTA in order to realize a small transconductance. The presented frequency synthesizer has the output frequency range from 570 MHz to 600 MHz with a 100 KHz frequency step. Total silicon area is about 0.3 mm2 using AMIS 0.5 ??m CMOS technology, and the power consumption is 26.7 mW with 3 V single power supply

Time-based control techniques for integrated DC-DC conversion

Time-based control techniques for the design of high switching frequency buck converters are presented. Using time as the processing variable, the proposed controller operates with CMOS-level digital-like signals but without adding any quantization error. A ring oscillator is used as an integrator in place of conventional opamp-RC or Gm-C integrators while a delay line is used to perform voltage-to-time conversion and to sum time signals. A simple flip-flop generates a pulse-width modulated signal from the time-based output of the controller. Hence time-based control eliminates the need for a wide bandwidth error amplifier, pulse width modulator (PWM) in analog controllers or high-resolution analog-to-digital converter (ADC) and digital PWM in digital controllers. As a result, it can be implemented in a small area and with minimal power. First, a time-based single-phase buck converter is proposed and fabricated in a 180nm CMOS process, the prototype buck converter occupies an active area of 0.24mm^2, of which the controller occupies only 0.0375mm^2. It operates over a wide range of switching frequencies (10-25 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V with 1.8V input voltage. With a 500mA step in the load current, the settling time is less than 3.5us and the measured reference tracking bandwidth is about 1MHz. Better than 94% peak efficiency is achieved while consuming a quiescent current of only 2uA/MHz. Second, the techniques are extended to a high switching frequency multi-phase buck converter. Efficiency degradation due to mismatch between the phases is mitigated by generating precisely matched duty-cycles by combining a time-based multi-phase generator (MPG) with a time-based PID compensator (T-PID). The proposed approach obviates the need for a complex current sensing and calibration circuitry needed to implement active current sharing in an analog controller. It also eliminates the need for a high-resolution analog-to-digital converter and digital pulse width modulator needed for implementing passive current sharing in a digital controller. Fabricated in a 65nm CMOS process, the prototype multi-phase buck converter occupies an active area of 0.32mm^2, of which the controller occupies only 0.04mm^2. The converter operates over a wide range of switching frequencies (30-70 MHz) and regulates output to any desired voltage in the range of 0.6V to 1.5V from 1.8V input voltage. With a 400mA step in the load current, the settling time is less than 0.6us and the measured duty-cycle mismatch is less than 0.48%. Better than 87% peak efficiency is achieved while consuming a quiescent current of only 3uA/MHz. Finally, light load operation is discussed. The light load efficiency of a time-based buck converter is improved by adding proposed PFM control. At the same time, the proposed seamless transition techniques provide a freedom to change the control mode between PFM and PWM without deteriorating output voltage which allows for a system to manage its power efficiently. Fabricated in a 65nm CMOS, the prototype achieves 90% peak efficiency and > 80% efficiency over an ILOAD range of 2mA to 800mA. VO changes by less than 40mV during PWM to PFM transitions

Development of a Detector Control System Chip

Der Large Hadron Collider (LHC) am CERN wird bis 2026 zum High-Luminosity LHC ausgebaut. Diese Erweiterung hat zum Ziel höhere Intensitäten bei den Kollisionen zu erreichen um die gesammelte Luminosität um einen Faktor 10 zu erhöhen. Mit dem grösseren Datensatz können die Eigenschaften des Standard Models der Teilchenphysik genauer vermessen werden. Die Experimente müssen dafür aktualisiert und aufgerüstet werden. Beim ATLAS Experiment wird der komplette innere Detektor für den Betrieb am High-Luminosity LHC mit einem neuen Silizium-Spurdetektor ersetzt. Dieser, ATLAS ITk Detektor genannt, besteht aus mehreren Lagen mit Pixel- und Streifensensoren. Für den ITk Pixeldetektor wird erstmals auch eine serielle Stromversorgung an einem LHC Experiment verwendet. Die serielle Versorgung hat den Vorteil, dass Leitungen und dadurch Material eingespart werden kann. Jedoch gibt es auch Risiken und neue Entwicklungen werden benötigt. Das Detektorkontrollsystem (DCS) hat die Aufgabe den Detektor und seinen Zustand zu überwachen. Das DCS kontrolliert auch den Betrieb des Detektors. Eine Integrierte Schaltung wurde speziell dazu entwickelt. Dieser Pixel Serial Power & Protection (PSPP) genannte Chip misst die Temperatur und Spannung von einem Modul in einer seriellen Versorgungskette. Weiter hat der Chip einen Bypass-Transistor, welcher das Modul kurzschliessen und damit deaktivieren kann. Das erlaubt es einzelne Module in der seriellen Versorgungskette zu steuern, während die anderen Module weiterhin funktionieren. Die Aktivierung des Bypasses kann automatisch erfolgen, sollte die Temperatur oder Spannung des Moduls zu gross werden. Auf Basis eines existierenden Prototyps wurden während dieser Arbeit weitere Versionen des PSPP entwickelt. Diese beinhalten alle benötigten Funktionen und können einen Strom von 8 A schalten. Der entwickelte PSPP wurde bis zu einer totalen ionisierenden Dosis von 800 Mrad erfolgreich getestet. Weiter wurden Tests der Resistenz gegenüber strahlenbasierten Bit-Flips durchgeführt. Es wurde ein Wirkungsquerschnitt kleiner 1.7 × 10⁻¹⁷ cm² gemessen. Ein Chip wurde auch in einer Klimakammer bei Temperaturen zwischen (0 und 60) °C während 42 Tagen erfolgreich betrieben. Während dieses Dauertests wurden keine Fehlfunktionen beobachtet. Der PSPP wurde ausserdem in einem Systemtest mit Sensormodulen und realistischer mechanischer Struktur eingesetzt. Die Funktion des PSPPs war hilfreich bei der Inbetriebnahme und Fehlersuche. Die automatische Bypass-Aktivierung bewahrte die Module vor Schäden. Mit Hilfe der vom PSPP gemessenen Daten wurde die Spezifikation der seriellen Versorgungskette verbessert.The Large Hadron Collider (LHC) at CERN will be updated to the High-Luminosity LHC by 2026. The goal of this update is to achieve higher intensities in the collisions and collect ten times more luminosity than with the LHC. This gives higher statistics to measure with greater precision the parameters of the standard model in particle physics. The ATLAS experiment will receive a completely new inner tracker for operation at the High-Luminosity LHC. This ATLAS ITk detector is a full silicon tracking detector with pixel and strip sensors. A serial power approach is foreseen for the ITk Pixel detector. This reduces the number of services and material, however, has also risks and new challenges. The task of the detector control system (DCS) is to monitor the health of the experiment and control the operation. An integrated circuit was developed for this task. The so-called pixel serial power & protection (PSPP) chip measures the voltage and temperature of a module in the serial power chain. Additionally, it includes a bypass transistor to deactivate a single module if necessary. The bypass is activated automatically in case of over-temperature or over-voltage. This gives full control over each module and allows to recover a serial power chain in case of a faulty module. Based on an existing prototype, new versions of the PSPP were developed for this thesis. They include all required functionalities and can switch a current of 8 A. The developed prototype is functional to a total integrated dose of 800 Mrad, which was tested in X-Ray irradiations. Further, tests were performed to verify the protection against single event upsets causing bit flips in the internal registers. The cross-section of the triplicated registers in the PSPP was measured with a proton test beam and is smaller than 1.7 × 10⁻¹⁷ cm² . The PSPP prototype successfully resisted temperatures between (0 and 60) °C in a 42-day long climate chamber test. No failure was observed. A system test with prototype modules was built at CERN to verify the concept of the serial power chain. This used realistic services and mechanical structures. The PSPP chip was included in the system test and proofed to be very useful during commissioning and debugging. The bypass and its protection function prevented damage to detector modules. The PSPP delivered useful monitoring data to refine the requirements of the serial power chain

A Reconfigurable Digital-to-Analog Converter with Supply Invariant Linearity

A novel reconfigurable digital-to-analog converter (DAC) with supply independent linearity is presented. The process agnostic converter achieves wide supply range operation and re-configurability by being charge based. This converter consists of a 7-bit parallel digital input control core and an analog summing core utilizing charging capacitors with an operational transconductance amplifier in a voltage-follower configuration. This topology is highly configurable to allow for optimization across process voltages, step sizes and low power operation. The specification of the DAC is (1) supply independence (2) low power operation (3) operation up to 200 kHz and (4) conversion control through a DAC enable signal. Supply independence is achieved through the use of a charge-based approach in the analog core utilizing a finite stepping voltage derived from another, much smaller, voltage reference. This voltage reference in turn determines the resolution of the DAC. The DAC will thus create a stair-stepping analog output until digital input is met or the voltage supply is reached. Feedback is utilized when either of these events occurs notifying the DAC to wait until another sample is requested. Low power is achieved by using static CMOS logic and the inclusion of a sleep mode in the analog core which can be used after the desired output is achieved. This design was implemented across two different processes with different power supplies to confirm the architecture

Integrated circuits for efficient power delivery using pulse-width-modulation

Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area. Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application. In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures. A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB. The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC). The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin

Ring amplification for switched capacitor circuits

A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail output swing, drive large capacitive loads with extreme efficiency using slew-based charging, naturally scale in performance according to process trends, and is simple enough to be quickly constructed from only a handful of inverters, capacitors, and switches. In addition, the gain-enhancement technique of Split-CLS is introduced, and used to extend the efficacy of ring amplifiers in specific and other amplifiers in general. Four different pipelined ADC designs are presented which explore the practical implementation options and design considerations relevant to ring amplification and Split-CLS, and are used to establish ring amplification as a new paradigm for scalable amplification

High-Speed Wide-Field Time-Correlated Single-Photon Counting Fluorescence Lifetime Imaging Microscopy

Fluorescence microscopy is a powerful imaging technique used in the biological sciences to identify labeled components of a sample with specificity. This is usually accomplished through labeling with fluorescent dyes, isolating these dyes by their spectral signatures with optical filters, and recording the intensity of the fluorescent response. Although these techniques are widely used, fluorescence intensity images can be negatively affected by a variety of factors that impact the fluorescence intensity. Fluorescence lifetime imaging microscopy (FLIM) is an imaging technique that is relatively immune to intensity fluctuations and also provides the unique ability to directly monitor the microenvironment surrounding a fluorophore. Despite the benefits associated with FLIM, the applications to which it is applied are fairly limited due to long image acquisition times and high cost of traditional hardware. Recent advances in complementary metal-oxide-semiconductor (CMOS) single-photon avalanche diodes (SPADs) have enabled the design of low-cost imaging arrays that are capable of recording lifetime images with acquisition times greater than one order of magnitude faster than existing systems. However, these SPAD arrays have yet to realize the full potential of the technology due to limitations in their ability to handle the vast amount of data generated during the commonly used time-correlated single-photon counting (TCSPC) lifetime imaging technique. This thesis presents the design, implementation, characterization, and demonstration of a high speed FLIM imaging system. The components of this design include a CMOS imager chip in a standard 0.13 μm technology containing a custom CMOS SPAD, a 64-by-64 array of these SPADs, pixel control circuitry, independent time-to-digital converters (TDCs), a FLIM specific datapath, and high bandwidth output buffers. In addition to the CMOS imaging array, a complete system was designed and implemented using a printed circuit board (PCB) for capturing data from the imager, creating histograms for the photon arrival data using field-programmable gate arrays, and transferring the data to a computer using a cabled PCIe interface. Finally, software is used to communicate between the imaging system and a computer.The dark count rate of the SPAD was measured to be only 231 Hz at room temperature while maintaining a photon detection probability of up to 30\%. TDCs included on the array have a 62.5 ps resolution and a 64 ns range, which is suitable for measuring the lifetime of most biological fluorophores. Additionally, the on-chip datapath was designed to handle continuous data transfers at rates capable of supporting TCSPC-based lifetime imaging at 100 frames per second. The system level implementation also provides sufficient data throughput for transferring up to 750 frames per second from the imaging system to a computer. The lifetime imaging system was characterized using standard techniques for evaluating SPAD performance and an electrical delay signal for measuring the TDC performance. This thesis concludes with a demonstration of TCSPC-FLIM imaging at 100 frames per second -- the fastest 64-by-64 TCSPC FLIM that has been demonstrated. This system overcomes some of the limitations of existing FLIM systems and has the potential to enable new application domains in dynamic FLIM imaging

A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme

An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for high-Q, high- frequency bandpass filter is proposed. The quality factor of the filter is tuned using a new quality factor locked loop algorithm. It was shown that a second-order quality factor locked loop is necessary and sufficient to tune the quality factor of a bandpass filter with zero steady state error. The accuracy, mismatch, and sensitivty analysis of the new tuning scheme was performed and analyzed. Based on the proposed noise optimized filter structure and new quality factor tuning scheme, a biquad filter was designed and fabricated in 0.25 μm BiCMOS process. The measured results show that the biquad filter achieves a SNR of 45 dB at IMD of 40 dB. The P-1dB compression point and IIP3 of the filter are -10 dBm and -2.68 dBm, respectively. The proposed biquad filter and quality factor tuning scheme consumes 58mW and 13 mW of power at 3.3 V supply.Ph.D.Committee Chair: Allen Phillip; Committee Member: Hasler Paul; Committee Member: Keezer David; Committee Member: Kenny James; Committee Member: Pan Ronghu

High-speed, economical design implementation of transit network router

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (p. 88-90).by Kazuhiro Hara.M.S