755 research outputs found

    Booth Multiplier Based on Low Power High Speed Full Adder With Fin_FET Technology

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    This paper proposes a novel Fin FET-based HSFA for the multiplier in order to overcome the issues of low speed operation. It is advantageous to use Fin FETs to construct the arithmetic circuit while assessing the available works. The carry propagation and slow operation of the old technique are disadvantages. The CMOS-based compressor circuit, on the other hand, suffers from leakage current, which reduces its driving capabilities. High current DSP applications are well matched to the design's specifications. Even with a supply voltage of 1 volt, the proposed device has a decent driving capability. As a result, the circuit runs more quickly and has less latency. A transmission gate is used in the design of the suggested adder structure to selectively block or transfer data from the input to output. Half adder and adder are shown in the following illustrations. The smaller the transistor count, the less power it uses. The suggested Fin FET design for the smaller transistors has a superior driving capability than the CMOS equivalent. Additionally, when cascading, the Fin FET based adder may contribute to superior switch performance, such as when using ripple carry adder. There is also the possibility of a low operation, which may operate at Low wattage Electronic designs for high-performance and small devices have become increasingly dependent on the use of VLSI circuits. The power of a processor is determined in large part by the multiplier used in its design. Multiplier factor booth coding is being used to reorder the input bits in order to reduce facility use. The booth decoder works by rearranging the specified booth equivalent. The Booth decoder has the ability to expand the range of zeros. As a result, the power consumption of the design will be decreased even more. As soon as the input bit constant drops below zero, related rows or columns of an adder must be disabled, if possible

    A Reconfigurable Digital Multiplier and 4:2 Compressor Cells Design

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    With the continually growing use of portable computing devices and increasingly complex software applications, there is a constant push for low power high speed circuitry to support this technology. Because of the high usage and large complex circuitry required to carry out arithmetic operations used in applications such as digital signal processing, there has been a great focus on increasing the efficiency of computer arithmetic circuitry. A key player in the realm of computer arithmetic is the digital multiplier and because of its size and power consumption, it has moved to the forefront of today\u27s research. A digital reconfigurable multiplier architecture will be introduced. Regulated by a 2-bit control signal, the multiplier is capable of double and single precision multiplication, as well as fault tolerant and dual throughput single precision execution. The architecture proposed in this thesis is centered on a recursive multiplication algorithm, where a large multiplication is carried out using recursions of simpler submultiplier modules. Within each sub-multiplier module, instead of carry save adder arrays, 4:2 compressor rows are utilized for partial product reduction, which present greater efficiency, thus result in lower delay and power consumption of the whole multiplier. In addition, a study of various digital logic circuit styles are initially presented, and then three different designs of 4:2 compressor in Domino Logic are presented and simulation results confirm the property of proposed design in terms of delay, power consumption and operation frequenc

    Crosstalk computing: circuit techniques, implementation and potential applications

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    Title from PDF of title [age viewed January 32, 2022Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (page 117-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2020This work presents a radically new computing concept for digital Integrated Circuits (ICs), called Crosstalk Computing. The conventional CMOS scaling trend is facing device scaling limitations and interconnect bottleneck. The other primary concern of miniaturization of ICs is the signal-integrity issue due to Crosstalk, which is the unwanted interference of signals between neighboring metal lines. The Crosstalk is becoming inexorable with advancing technology nodes. Traditional computing circuits always tries to reduce this Crosstalk by applying various circuit and layout techniques. In contrast, this research develops novel circuit techniques that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. This research work presents a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model. Along with regular digital logic circuits, it also presents a novel Polymorphic circuit approach unique to Crosstalk Computing. In Polymorphic circuits, the functionality of a circuit can be altered using a control variable. Owing to the multi-functional embodiment in polymorphic-circuits, they find many useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. This dissertation shows a comprehensive list of polymorphic logic gate implementations, which were not reported previously in any other work. It also performs a comparison study between Crosstalk polymorphic circuits and existing polymorphic approaches, which are either inefficient due to custom non-linear circuit styles or propose exotic devices. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation and characterization results show a 6x improvement in transistor count, 2x improvement in switching energy, and 1.5x improvement in performance compared to counterpart implementation in CMOS circuit style. Nevertheless, the Crosstalk circuits also face issues while cascading the circuits; this research analyzes all the problems and develops auxiliary circuit techniques to fix the problems. Moreover, it shows a module-level cascaded polymorphic circuit example, which also employs the auxiliary circuit techniques developed. For the very first time, it implements a proof-of-concept prototype Chip for Crosstalk Computing at TSMC 65nm technology and demonstrates experimental evidence for runtime reconfiguration of the polymorphic circuit. The dissertation also explores the application potentials for Crosstalk Computing circuits. Finally, the future work section discusses the Electronic Design Automation (EDA) challenges and proposes an appropriate design flow; besides, it also discusses ideas for the efficient implementation of Crosstalk Computing structures. Thus, further research and development to realize efficient Crosstalk Computing structures can leverage the comprehensive circuit framework developed in this research and offer transformative benefits for the semiconductor industry.Introduction and Motivation -- More Moore and Relevant Beyond CMOS Research Directions -- Crosstalk Computing -- Crosstalk Circuits Based on Perception Model -- Crosstalk Circuit Types -- Cascading Circuit Issues and Sollutions -- Existing Polymorphic Circuit Approaches -- Crosstalk Polymorphic Circuits -- Comparison and Benchmarking of Crosstalk Gates -- Practical Realization of Crosstalk Gates -- Poential Applications -- Conclusion and Future Wor

    VLSI design methodology

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    Design considerations for a monolithic, GaAs, dual-mode, QPSK/QASK, high-throughput rate transceiver

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    A monolithic, GaAs, dual mode, quadrature amplitude shift keying and quadrature phase shift keying transceiver with one and two billion bits per second data rate is being considered to achieve a low power, small and ultra high speed communication system for satellite as well as terrestrial purposes. Recent GaAs integrated circuit achievements are surveyed and their constituent device types are evaluated. Design considerations, on an elemental level, of the entire modem are further included for monolithic realization with practical fabrication techniques. Numerous device types, with practical monolithic compatability, are used in the design of functional blocks with sufficient performances for realization of the transceiver

    Serial-data computation in VLSI

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    Real-time Prediction of Cascading Failures in Power Systems

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    Blackouts in power systems cause major financial and societal losses, which necessitate devising better prediction techniques that are specifically tailored to detecting and preventing them. Since blackouts begin as a cascading failure (CF), an early detection of these CFs gives the operators ample time to stop the cascade from propagating into a large-scale blackout. In this thesis, a real-time load-based prediction model for CFs using phasor measurement units (PMUs) is proposed. The proposed model provides load-based predictions; therefore, it has the advantages of being applicable as a controller input and providing the operators with better information about the affected regions. In addition, it can aid in visualizing the effects of the CF on the grid. To extend the functionality and robustness of the proposed model, prediction intervals are incorporated based on the convergence width criterion (CWC) to allow the model to account for the uncertainties of the network, which was not available in previous works. Although this model addresses many issues in previous works, it has limitations in both scalability and capturing of transient behaviours. Hence, a second model based on recurrent neural network (RNN) long short-term memory (LSTM) ensemble is proposed. The RNN-LSTM is added to better capture the dynamics of the power system while also giving faster responses. To accommodate for the scalability of the model, a novel selection criterion for inputs is introduced to minimize the inputs while maintaining a high information entropy. The criteria include distance between buses as per graph theory, centrality of the buses with respect to fault location, and the information entropy of the bus. These criteria are merged using higher statistical moments to reflect the importance of each bus and generate indices that describe the grid with a smaller set of inputs. The results indicate that this model has the potential to provide more meaningful and accurate results than what is available in the previous literature and can be used as part of the integrated remedial action scheme (RAS) system either as a warning tool or a controller input as the accuracy of detecting affected regions reached 99.9% with a maximum delay of 400 ms. Finally, a validation loop extension is introduced to allow the model to self-update in real-time using importance sampling and case-based reasoning to extend the practicality of the model by allowing it to learn from historical data as time progresses

    Design and Analysis of Improved Domino Logic with Noise Tolerance and High Performance

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    The demands of upcoming computing, as well as the challenges of nanometer-era of VLSI design necessitate new digital logic techniques and styles that are at the same time high performance, energy efficient and robust to noise and variation. Dynamic CMOS logic gates are broadly used to design high performance circuits due to their high speed. Conversely, the vital demerit of dynamic logic style is its high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the pull down network. With continuous technology scaling, this problem is getting more and more severe. In this thesis, a new noise tolerant dynamic CMOS circuit technique is proposed. In the proposed work, we have enhanced the behavior of the domino CMOS logic. This technique also gets benefit in terms of delay and power. This thesis describes the new low power, noise tolerant and high speed domino logic technique and presents a comparison result of this logic with previously reported schemes. Simulation results prove that, in 180 nm CMOS technology when we used this logic style to realize wide fan-in logic gates, it could achieve maximum level of noise robustness as compared to its basic counterpart. In addition, the logic also works efficiently with sequential circuits. The feasibility of this new technique is demonstrated by means of a real hardware, we have built a custom test-chip in the UMC 180 nm process technology with an ALU core, using the proposed domino logic style for each design block. In this thesis, we have also described the design and implementation of this chip. In addition to this, we have also presented initial power and delay performance comparisons between the circuit level simulated ALU and test-chip implemented in the proposed domino logic style. Finally we conclude that, the thesis contributes a very efficient logic style for wide fan-in gates, which is not only noise robust but also energy efficient and high speed

    Gallium arsenide bit-serial integrated circuits

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