Heterogeneous Integration of RF and Microwave Systems Using Multi-layer Low-Temperature Co-fired Ceramics Technology

[eng] The aim of this work is the development of a modelling methodology for the fast analysis of non-radiative multilayer RF passive components without compromising solution accuracy. Instead of following a compact model approach, oftenly used in integrated technologies, the method is based on a specialized quasi-static partial element equivalent circuit (PEEC) numerical solver. Besides speed and accuracy, the solver can be embedded in circuit simulators; thus, models are already available in the schematic entry. Using this framework, model scalability is enhanced in terms of geometry, substrate cross-section, material properties, topology and boundary conditions. The dissertation starts showing the actual performance of the obtained solver and the motivations beneath its development. Then, the description about solver development is splitted in three parts, but all of them are interrelated. First, the PEEC formulation is adapted according to relevant electromagnetic behaviour of the component. It is worth stressing that a different perspective related to the principle of virtual work is used in this formulation. The second part deals with the evaluation of partial elements, the core of the solver. It is carried out using analytical space-domain close-form solutions of the Green’s function (GF) of the substrate. Partial elements are then assembled into a mesh. Therefore, the importance of the mesh up on solution accuracy is discussed in the last part and a basic layout aware mesh generator is proposed. Practical application of the methodology includes the implementation of a library of RF passives for multilayer substrate. For validation, the chosen substrate is a low temperature co-fired ceramics (LTCC) technology. Different set of devices have been fabricated, characterized and compared against model prediction. In addition, the obtained results are also verified using state-of-the-art electromagnetic solvers.[spa] El objetivo de este trabajo es el desarrollo de una metodología de modelado para el análisis rápido, pero sin comprometer la precisión de la solución, de componentes pasivos no radiativos de RF en substratos multicapa. El método se basa en el algoritmo numérico cuasi-estático de los elementos parciales de circuito equivalente (PEEC). Éste puede ser incorporado en simuladores de circuitos; por tanto, los modelos ya están disponibles en la entrada de esquemático de forma transparente para el diseñador de circuitos. Utilizando este marco, la escalabilidad del modelo se mejora en términos de la geometría, la definición del corte tecnológico, las propiedades del material, la topología del componente y las condiciones de contorno electro-magnéticas. Esta disertación comienza mostrando las motivaciones que han llevado a su desarrollo y la capacidad real del método de resolución obtenido. A partir de aquí, se realiza la descripción de todo el desarrollo del marco numérico que se divide en tres partes que están interrelacionadas. En primer lugar, la formulación PEEC se adapta según el comportamiento electromagnético real del componente. Vale la pena subrayar que en esta formulación se utiliza una perspectiva diferente a la habitual y que está relacionada con el principio de los trabajos virtuales de d’Alembert. La segunda parte trata de cómo se evalúan los elementos parciales y constituye el núcleo principal del algoritmo. Se lleva a cabo utilizando soluciones analíticas de la función de Green (GF) del sustrato en el dominio espacial. Los elementos parciales, que forman la malla numérica del modelo, se ensamblan en la matriz del sistema siguiendo un procedimiento de análisis nodal modificado (MNA). En la última parte, se discute la importancia de la malla sobre la precisión de la solución y se propone un generador de malla basado en la física del componente y no sólo en la descripción de la geometría. Como aplicación práctica de la metodología, se realiza la generación de una biblioteca de componentes pasivos RF para sustratos multicapa

Electromagnetic Interference and Compatibility

Recent progress in the fields of Electrical and Electronic Engineering has created new application scenarios and new Electromagnetic Compatibility (EMC) challenges, along with novel tools and methodologies to address them. This volume, which collects the contributions published in the “Electromagnetic Interference and Compatibility” Special Issue of MDPI Electronics, provides a vivid picture of current research trends and new developments in the rapidly evolving, broad area of EMC, including contributions on EMC issues in digital communications, power electronics, and analog integrated circuits and sensors, along with signal and power integrity and electromagnetic interference (EMI) suppression properties of materials

Batteries and Supercapacitors Aging

Electrochemical energy storage is a key element of systems in a wide range of sectors, such as electro-mobility, portable devices, and renewable energy. The energy storage systems (ESSs) considered here are batteries, supercapacitors, and hybrid components such as lithium-ion capacitors. The durability of ESSs determines the total cost of ownership, the global impacts (lifecycle) on a large portion of these applications and, thus, their viability. Understanding ESS aging is a key to optimizing their design and usability in terms of their intended applications. Knowledge of ESS aging is also essential to improve their dependability (reliability, availability, maintainability, and safety). This Special Issue includes 12 research papers and 1 review article focusing on battery, supercapacitor, and hybrid capacitor aging

Supercapacitors (electrochemical capacitors)

International audienceRapid development of the technologies based on electric energy in the last decades have stimulated intensive research on efficient power sources. Electrochemical energy conversion and storage systems are based on Faradaic reactions (charge transfer) and electrostatic attraction of ions at the electrode/electrolyte interface. The latter might be an interesting solution for applications requiring moderate energy density, high power rates, and long cycle life. Electrochemical capacitors (ECs) store the charge in a physical manner, hence, their energy density is moderate. At the same time, the lack of electrochemical reactions ensures very high power and long cycle life compared to batteries. Activated carbons with their versatile properties (like specific surface area, well-developed and suitable porosity, heteroatoms in the graphene matrix) are the most popular materials in EC application. This chapter provides a comprehensive overview of the carbon-based materials recently developed, with special attention devoted to those obtained by biomass carbonization and activation. Electrochemical properties demonstrated by such carbons are discussed in respect to their physicochemical characteristic

Design and Implementation of an Integrated Biosensor Platform for Lab-on-a-Chip Diabetic Care Systems

Recent advances in semiconductor processing and microfabrication techniques allow the implementation of complex microstructures in a single platform or lab on chip. These devices require fewer samples, allow lightweight implementation, and offer high sensitivities. However, the use of these microstructures place stringent performance constraints on sensor readout architecture. In glucose sensing for diabetic patients, portable handheld devices are common, and have demonstrated significant performance improvement over the last decade. Fluctuations in glucose levels with patient physiological conditions are highly unpredictable and glucose monitors often require complex control algorithms along with dynamic physiological data. Recent research has focused on long term implantation of the sensor system. Glucose sensors combined with sensor readout, insulin bolus control algorithm, and insulin infusion devices can function as an artificial pancreas. However, challenges remain in integrated glucose sensing which include degradation of electrode sensitivity at the microscale, integration of the electrodes with low power low noise readout electronics, and correlation of fluctuations in glucose levels with other physiological data. This work develops 1) a low power and compact glucose monitoring system and 2) a low power single chip solution for real time physiological feedback in an artificial pancreas system. First, glucose sensor sensitivity and robustness is improved using robust vertically aligned carbon nanofiber (VACNF) microelectrodes. Electrode architectures have been optimized, modeled and verified with physiologically relevant glucose levels. Second, novel potentiostat topologies based on a difference-differential common gate input pair transimpedance amplifier and low-power voltage controlled oscillators have been proposed, mathematically modeled and implemented in a 0.18μm [micrometer] complementary metal oxide semiconductor (CMOS) process. Potentiostat circuits are widely used as the readout electronics in enzymatic electrochemical sensors. The integrated potentiostat with VACNF microelectrodes achieves competitive performance at low power and requires reduced chip space. Third, a low power instrumentation solution consisting of a programmable charge amplifier, an analog feature extractor and a control algorithm has been proposed and implemented to enable continuous physiological data extraction of bowel sounds using a single chip. Abdominal sounds can aid correlation of meal events to glucose levels. The developed integrated sensing systems represent a significant advancement in artificial pancreas systems

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.Siirretty Doriast

Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology

Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes is difficult or cumbersome. This thesis proposes a design of an RF energy harvesting device able to charge commercially available thin film or solid-state batteries. The energy harvesting amplifier circuit is designed in Global Foundry 0.13um CMOS technology using Cadence integrated circuit design tools. This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, harvesting ambient RF power from TV and UHF cellular frequencies increases the possibilities of where the harvesting device can be placed. The biggest challenge for RF energy harvesting technology is the availability of adequate amount of RF power. This thesis also presents a survey of available RF power at various ultra-high frequencies in San Luis Obispo, CA.The idea is to determine the frequency band which can provide maximum RF power for harvesting and design a harvester for that frequency band

Can my chip behave like my brain?

Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.Ph.D