Characterization of a CMUT Array

Ultrasound transducers are used in a broad range of applications covering from underwater communications to medical imaging and treatment. The ultrasonic transducer determines the key specifications such as resolution, sensitivity and signal to noise ratio. The capacitive micromachined ultrasonic transducer (CMUT) has emerged as an alternative to standard piezoelectric transducers due to advanced microelectronics fabrication technology and methods. Comparing to piezoelectric transducers, the CMUT is superior to it\u27s competitor with higher acoustic bandwidth, higher sensitivity and greater coupling with the acoustic medium. Design, fabrication, and characterization of a capacitive micromachined ultrasonic transducer (CMUT) array have been presented along this thesis. The array is designed to operate in the frequency range of 113-167 kHz. The CMUT array is fabricated using an SOI based fabrication technology and includes 6x6 CMUTs. Necessary test setups and readout circuitry is designed in order to carry out the characterization process. Static analysis results are verified with Wyko optical profilometer, Agilent LCR meter and SEM analysis. Dynamic characterizations are done with Polytec MSA-4 laser Doppler vibrometer. An efficient and low noise capacitive readout circuit is designed using transimpedance amplifier scheme with 75 kilo ohm gain and fabricated on a PCB. The developed analytical models, FEA and experimental results are in very good agreement to exhibit accuracy of the design methodology

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

3D modeling and integration of current and future interconnect technologies

Title from PDF of title page viewed June 21, 2021Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 133-138)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2021To ensure maximum circuit reliability it is very important to estimate the circuit performance and signal integrity in the circuit design phase. A full phase simulation for performance estimation of a large-scale circuit not only require a massive computational resource but also need a lot of time to produce acceptable results. The estimation of performance/signal integrity of sub-nanometer circuits mostly depends on the interconnect capacitance. So, an accurate model for interconnect capacitance can be used in the circuit CAD (computer-aided design) tools for circuit performance estimation before circuit fabrication which reduces the computational resource requirement as well as the time constraints. We propose a new capacitance models for interconnect lines in multilevel interconnect structures by geometrically modeling the electrical flux lines of the interconnect lines. Closed-form equations have been derived analytically for ground and coupling capacitance. First, the capacitance model for a single line is developed, and then the new model is used to derive expressions for the capacitance of a line surrounded by neighboring lines in the same and the adjacent layers above and below. These expressions are simple, and the calculated results are within 10% of Ansys Q3D extracted values. Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major challenges of 3D integration. In this paper, different materials for the cores of the vias and the interposers are investigated to find the best possible combination that can reduce crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored glass and silicon as interposer materials. The simulation results indicate that glass is the best option as interposer material although silicon interposer has some distinct advantages. For via cores three materials - copper (Cu), tungsten (W) and Cu-W bimetal are considered. From the analysis it can concluded that W would be better for high frequency applications due to lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be in between Cu and W. However, W has a thermal expansion coefficient close to silicon. Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission coefficient and crosstalk in the vias. Signal speed in current digital systems depends mainly on the delay of interconnects. To overcome this delay problem and keep up with Moore’s law, 3D integrated circuit (vertical integration of multiple dies) with through-silicon via (TSV) has been introduced to ensure much smaller interconnect lengths, and lower delay and power consumption compared to conventional 2D IC technology. Like 2D circuit, the estimation of 3D circuit performance depends on different electrical parameters (capacitance, resistance, inductance) of the TSV. So, accurate modeling of the electrical parameters of the TSV is essential for the design and analysis of 3D ICs. We propose a set of new models to estimate the capacitance, resistance, and inductance of a Cu-filled TSV. The proposed analytical models are derived from the physical shape and the size of the TSV. The modeling approach is comprehensive and includes both the cylindrical and tapered TSVs as well as the bumps. On-chip integration of inductors has always been very challenging. However, for sub- 14nm on-chip applications, large area overhead imposed by the on-chip capacitors and inductors has become a more severe concern. To overcome this issue and ensure power integrity, a novel 3D Through-Silicon-Via (TSV) based inductor design is presented. The proposed TSV based inductor has the potential to achieve both high density and high performance. A new design of a Voltage Controlled Oscillator (VCO) utilizing the TSV based inductor is also presented. The implementation of the VCO is intended to study the feasibility, performance, and real-world application of the proposed TSV based inductor.Introduction -- Background of capacitance modeling of on-chip interconnect -- Accurate modeling of interconnect capacitance in multilevel interconnect structures for sub 22nm technology -- Analysis of different materials and structures for through silicon via and through glass via in 3D integrated circuits -- Impacts of different shapes of through-silicon-via core on 3D IC performance -- Accurate electrical modeling of cu-filled through-silicon-via (TSV) -- Design and characterize TSV based inductor for high frequency voltage-controlled oscillator design -- Conclusion and future wor

Developing ultrasensitive and CMOS compatible ISFETs in the BEOL of industrial UTBB FDSOI transistors

Le marché des capteurs a récemment connu une croissance spectaculaire alimentée par l'application remarquable de capteurs dans l'électronique de consommation, l'industrie de l'automatisation, les appareils portables, le secteur automobile et l'internet des objets de plus en plus adopté. La technologie avancée des complementary metal oxide semiconductor (CMOS), les technologies de nano et de micro-fabrication et les plateformes de synthèse de matériaux innovantes sont également des moteurs du développement incroyable de l'industrie des capteurs. Ces progrès ont permis la réalisation de capteurs dotés de nombreuses caractéristiques telles que la précision accrue, les dimensions miniaturisées, l’intégrabilité, la production de masse, le coût très réduit et le temps de réponse rapide. Les ion-sensitive field-effect transistors (ISFETs) sont des capteurs à l'état solide (bio) chimiques, destinés à la détection des ions H+ (pH), Na+ et K+. Malgré cela, la commercialisation des ISFETs est encore à ses balbutiements, après près de cinq décennies de recherche et développement. Cela est dû principalement à la sensibilité limitée, à la controverse sur l'utilisation de l'électrode de référence pour le fonctionnement des ISFETs et à des problèmes de stabilité. Dans cette thèse, les ISFETs ultrasensibles et compatibles CMOS sont intégrés dans le BEOL des transistors UTBB FDSOI standard. Un circuit diviseur capacitif est utilisé pour polariser la grille d’avant afin d'assurer des performances stables du capteur. En exploitant la fonction d’amplification intrinsèque fournie par les transistors UTBB FDSOI, nous avons présenté des ISFET ultra sensibles. L'amplification découle du fort couplage électrostatique entre la grille avant et la grille arrière du FDSOI et des capacités asymétriques des deux grilles. Un changement de tension au niveau de la grille avant apparaît sur la grille arrière sous la forme d'un décalage amplifié de la tension. L'amplification, représentée par le facteur de couplage (γ), est égale au rapport de la capacité de l'oxyde de grille et de la capacité de le buried oxide (BOX). Par conséquent, en fonctionnalisant la détection du pH sur la grille avant pour les dispositifs FDSOI, la modification du potentiel de surface sur la grille avant est détectée par la grille arrière et amplifiée du facteur de couplage (γ), donnant lieu à un capteur chimique à l'état solide à sensibilité ultra-élevée. L'intégration de la fonctionnalité de détection a été réalisée en back end of line (BEOL), ce qui offre les avantages d'une fiabilité et d'une durée de vie accrues du capteur, d'une compatibilité avec le processus CMOS standard et d'une possibilité d'intégration d'un circuit diviseur capacitif. Le fonctionnement des MOSFETs, sans une polarisation appropriée de la grille avant, les rend vulnérables aux effets de grilles flottantes indésirables. Le circuit diviseur capacitif résout ce problème en polarisant la grille avant tout enmaintenant la fonctionnalité de détection sur la même grille par un couplage capacitif au métal commun du BEOL. Par conséquent, le potentiel au niveau du métal BEOL est une somme pondérée du potentiel de surface au niveau de la grille de détection et de la polarisation appliquée au niveau de la grille de contrôle. Le capteur proposé est modélisé et simulé à l'aide de TCAD-Sentaurus. Un modèle mathématique complet a été développé. Il fournit la réponse du capteur en fonction du pH de la solution (entrée du capteur) et des paramètres de conception du circuit diviseur capacitif et du transistor UTBB FDSOI. Dans ce cas, des résultats cohérents ont été obtenus des travaux de modélisation et de simulation, avec une sensibilité attendue de 780 mV / pH correspondant à un film de détection ayant une réponse de Nernst. La modélisation et la simulation du capteur proposé ont également été validées par une fabrication et une caractérisation du capteur de pH à grille étendue avec validation de son concept. Ces capteurs ont été développés par un traitement séparé du composant de détection de pH, qui est connecté électriquement au transistor uniquement lors de la caractérisation du capteur. Ceci permet une réalisation plus rapide et plus simple du capteur sans avoir besoin de masques et de motifs par lithographie. Les capteurs à grille étendue ont présenté une sensibilité de 475 mV/pH, ce qui est supérieur aux ISFET de faible puissance de l'état de l’art. Enfin, l’intégration de la fonctionnalité de détection directement dans le BEOL des dispositifs FDSOI UTBB a été poursuivie. Une sensibilité expérimentale de 730 mV/pH a été obtenue, ce qui confirme le modèle mathématique et la réponse simulée. Cette valeur est 12 fois supérieure à la limite de Nernst et supérieure aux capteurs de l'état de l’art. Les capteurs sont également évalués pour la stabilité, la résolution, l'hystérésis et la dérive dans lesquels d'excellentes performances sont démontrées. Une nouvelle architecture de détection du pH est également démontrée avec succès, dans laquelle la détection est fonctionnalisée au niveau de la diode de protection de la grille plutôt que de la grille avant des dispositifs UTBB FDSOI. La commutation de courant abrupte, aussi basse que 9 mV/decade, pourrait potentiellement augmenter la sensibilité de polarisation fixée à 6,6 decade/pH. Nous avons démontré expérimentalement une sensibilité de 1,25 decade/pH supérieure à la sensibilité reportée à l’état de l’art.Abstract: The sensor market has recently seen a dramatic growth fueled by the remarkable application of sensors in the consumer electronics, automation industry, wearable devices, the automotive sector, and in the increasingly adopted internet of things (IoT). The advanced complementary metal oxide semiconductor (CMOS) technology, the nano and micro fabrication technologies, and the innovative material synthesis platforms are also driving forces for the incredible development of the sensor industry. These technological advancements have enabled realization of sensors with characteristic features of increased accuracy, miniaturized dimension, integrability, volume production, highly reduced cost, and fast response time. Ion-sensitive field-effect transistors (ISFETs) are solid state (bio)chemical sensors, for pH (H+), Na+, K+ ion detection, that are equipped with the promise of the highly aspired features of CMOS devices. Despite this, the commercialization of ISFETs is still at the stage of infancy after nearly five decades of research and development. This is due mainly to the limited sensitivity, the controversy over the use of the reference electrode for ISFET operation, and because of stability issues. In this thesis, ultrasensitive and CMOS compatible ISFETs are integrated in the back end of line (BEOL) of standard UTBB FDSOI transistors. A capacitive divider circuit is employed for biasing the front gate for stable performance of the sensor. Exploiting the intrinsic amplification feature provided by UTBB FDSOI transistors, we demonstrated ultrahigh sensitive ISFETs. The amplification arises from the strong electrostatic coupling between the front gate and the back gate of the FDSOI, and the asymmetric capacitances of the two gates. A change in voltage at the front gate appears at the back gate as an amplified shift in voltage. The amplification, referred to as the coupling factor (γ), is equal to the ratio of the gate oxide capacitance and the buried oxide (BOX) capacitance. Therefore, functionalizing the pH sensing at the front gate of FDSOI devices, the change in surface potential at the front gate is detected at the back gate amplified by the coupling factor (γ), giving rise to an ultrahigh-sensitive solid state chemical sensor. Integration of the sensing functionality was made in the BEOL which gives the benefits of increased reliability and life time of the sensor, compatibility with the standard CMOS process, and possibility for embedding a capacitive divider circuit. Operation of the MOSFETs without a proper front gate bias makes them vulnerable for undesired floating body effects. The capacitive divider circuit addresses these issues by biasing the front gate simultaneously with the sensing functionality at the same gate through capacitive coupling to a common BEOL metal. Therefore, the potential at the BEOL metal would be a weighted sum of the surface potential at the sensing gate and the applied bias at the control gate. The proposed sensor is modeled and simulated using TCAD-Sentaurus. A complete mathematical model is developed which provides the output of the sensor as a function of the solution pH (input to the sensor), and the design parameters of the capacitive divider circuit and the UTBB FDSOI transistor. In that case, consistent results have been obtained from the modeling and simulation works, with an expected sensitivity of 780 mV/pH corresponding to a sensing film having Nernst response. The modeling and simulation of the proposed sensor was further validated by a proof of concept extended gate pH sensor fabrication and characterization. These sensors were developed by a separated processing of just the pH sensing component, which is electrically connected to the transistor only during characterization of the sensor. This provides faster and simpler realization of the sensor without the need for masks and patterning by lithography. The extended gate sensors showed 475 mV/pH sensitivity which is superior to state of the art low power ISFETs. Finally, integration of the sensing functionality directly in the BEOL of the UTBB FDSOI devices was pursued. An experimental sensitivity of 730 mV/pH is obtained which is consistent with the mathematical model and the simulated response. This is more than 12-times higher than the Nernst limit, and superior to state of the art sensors. Sensors are also evaluated for stability, resolution, hysteresis, and drift in which excellent performances are demonstrated. A novel pH sensing architecture is also successfully demonstrated in which the detection is functionalized at the gate protection diode rather than the front gate of UTBB FDSOI devices. The abrupt current switching, as low as 9 mV/decade, has the potential to increase the fixed bias sensitivity to 6.6 decade/pH. We experimentally demonstrated a sensitivity of 1.25 decade/pH which is superior to the state of the art sensitivity

Analysis of Crosstalk Noise for 2π RC Model considering Interconnect Parameters in Deep Submicron VLSI Circuit

As the technology enters into deep sub-micron region, signal integrity is becoming a very crucial parameter. In order to deal with the challenges associated with signal integrity problem, such as, crosstalk noise and delay, estimation and minimizing techniques should be addressed with great importance. Along with this, the peak noise amplitude and noise width values in the sensitive node must be verified and confirmed that they are below the certain threshold levels. Hence, for a particular range of frequency, an accurate and efficient crosstalk noise estimation model is necessary to confirm the signal integrity. Therefore, this work aims to analyse the crosstalk noise between two interconnect lines using 2π RC model, and considering its physical parameters, such as the parasitic capacitance, resistance and inductance and interconnect parameters, specifically the spacing between two interconnects, length, width, thickness, height from substrate in deep sub-micron VLSI circuit. In this paper, analytical expressions for peak noise amplitude and noise width in 2π model with RC interconnects for unit step input were derived, and then it was simulated in MATLAB and HSPICE software platform. The MATLAB based results represent that 2π model possesses less errors, and showed better performance compared to some other popular models by adjusting the interconnecting parameters for any certain range of operating frequency. The HSPICE simulation justifies the accuracy of the approach with full satisfaction

Plasmonic Metamaterials: Physical Background and Some Technological Applications

New technological frontiers appear every year, and few are as intriguing as the field of plasmonic metamaterials (PMMs). These uniquely designed materials use coherent electron oscillations to accomplish an astonishing array of tasks, and they present diverse opportunities in many scientific fields. This paper consists of an explanation of the scientific background of PMMs and some technological applications of these fascinating materials. The physics section addresses the foundational concepts necessary to understand the operation of PMMs, while the technology section addresses various applications, like precise biological and chemical sensors, cloaking devices for several frequency ranges, nanoscale photovoltaics, experimental optical computing components, and superlenses that can surpass the diffraction limit of conventional optics

High Speed Test Interface Module Using MEMS Technology

With the transient frequency of available CMOS technologies exceeding hundreds of gigahertz and the increasing complexity of Integrated Circuit (IC) designs, it is now apparent that the architecture of current testers needs to be greatly improved to keep up with the formidable challenges ahead. Test requirements for modern integrated circuits are becoming more stringent, complex and costly. These requirements include an increasing number of test channels, higher test-speeds and enhanced measurement accuracy and resolution. In a conventional test configuration, the signal path from Automatic Test Equipment (ATE) to the Device-Under-Test (DUT) includes long traces of wires. At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. The effects on transmission lines become critical requiring impedance matching to minimize signal reflection. AC resistance due to the skin effect and electromagnetic coupling caused by radiation can also become important factors affecting the test results. In the design of a Device Interface Board (DIB), the greater the physical separation of the DUT and the ATE pin electronics, the greater the distortion and signal degradation. In this work, a new Test Interface Module (TIM) based on MEMS technology is proposed to reduce the distance between the tester and device-under-test by orders of magnitude. The proposed solution increases the bandwidth of test channels and reduces the undesired effects of transmission lines on the test results. The MEMS test interface includes a fixed socket and a removable socket. The removable socket incorporates MEMS contact springs to provide temporary with the DUT pads and the fixed socket contains a bed of micro-pins to establish electrical connections with the ATE pin electronics. The MEMS based contact springs have been modified to implement a high-density wafer level test probes for Through Silicon Vias (TSVs) in three dimensional integrated circuits (3D-IC). Prototypes have been fabricated using Silicon On Insulator SOI wafer. Experimental results indicate that the proposed architectures can operate up to 50 GHz without much loss or distortion. The MEMS probes can also maintain a good elastic performance without any damage or deformation in the test phase

Contactless Test Access Mechanism for 3D IC

3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size while supporting higher bandwidth and processing speed. Through Silicon Via’s (TSVs) are vertical interconnects between different layers of 3D ICs with a typical 5μm diameter and 50μm length. To test a 3D IC, an access mechanism is needed to apply test vectors to TSVs and observe their responses. However, TSVs are too small for access by current wafer probes and direct TSV probing may affect their physical integrity. In addition, the probe needles for direct TSV probing must be cleaned or replaced frequently. Contactless probing method resolves most of the TSV probing problems and can be employed for small-pitch TSVs. In this dissertation, contactless test access mechanisms for 3D IC have been explored using capacitive and inductive coupling techniques. Circuit models for capacitive and inductive communication links are extracted using 3D full-wave simulations and then circuit level simulations are carried out using Advanced Design System (ADS) design environment to verify the results. The effects of cross-talk and misalignment on the communication link have been investigated. A contactless TSV probing method using capacitive coupling is proposed and simulated. A prototype was fabricated using TSMC 65nm CMOS technology to verify the proposed method. The measurement results on the fabricated prototype show that this TSV probing scheme presents -55dB insertion loss at 1GHz frequency and maintains higher than 35dB signal-to-noise ratio within 5µm distance. A microscale contactless probe based on the principle of resonant inductive coupling has also been designed and simulated. Experimental measurements on a prototype fabricated in TSMC 65nm CMOS technology indicate that the data signal on the TSV can be reconstructed when the distance between the TSV and the probe remains less than 15µm

Energy-efficient memcapacitor devices for neuromorphic computing

Data-intensive computing operations, such as training neural networks, are essential for applications in artificial intelligence but are energy intensive. One solution is to develop specialized hardware onto which neural networks can be directly mapped, and arrays of memristive devices can, for example, be trained to enable parallel multiply–accumulate operations. Here we show that memcapacitive devices that exploit the principle of charge shielding can offer a highly energy-efficient approach for implementing parallel multiply–accumulate operations. We fabricate a crossbar array of 156 microscale memcapacitor devices and use it to train a neural network that could distinguish the letters ‘M’, ‘P’ and ‘I’. Modelling these arrays suggests that this approach could offer an energy efficiency of 29,600 tera-operations per second per watt, while ensuring high precision (6–8 bits). Simulations also show that the devices could potentially be scaled down to a lateral size of around 45 nm