3,243 research outputs found

    Low-Power, High-Speed Transceivers for Network-on-Chip Communication

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    Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

    A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS

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    This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents (below 10 /spl mu/A) than other previous nonlinear feedback comparators. Particularly, when compared to the fastest current comparator reported up to now, the new one operates at more that 100 times faster for a 1 nA current, with smaller area occupation and similar power consumption. In addition, the new comparator is virtually insensitive to mismatch and capable of operating with supply voltages as low as 1 V

    Repeater insertion to minimise delay in coupled interconnects.

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    Signalling over long interconnect is a dominant issue in electronic chip design in current technologies, with the device sizes getting smaller and smaller and the circuits becoming ever larger. Repeater insertion is a well established technique to minimise the propagation delay over long resistive interconnect. In deep sub-micron technologies, as the wires are spaced closer and closer together and signal rise and fall times go into the sub-nano second region, the coupling between interconnects assumes great significance. The resulting crosstalk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. In this paper we attempt to quantify the effect of worst-case capacitive crosstalk in parallel buses and look at how it affects repeater insertion in particular. We develop analytic expressions for the delay, buffer size and number that are suitable in a-priori timing analyses and signal integrity estimations. All equations are checked against a dynamic circuit simulator (SPECTRE

    Additivity of Capacitive and Inductive Coupling in Submicronic Interconnects

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    International audienceConstant evolution in integrated circuit technology has led to an increase in the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. Inductive coupling effects on interconnects is an emerging concern in high performance digital integrated circuits. Based on an RLC transmission line model, associated to each propagation mode, a new crosstalk noise model is proposed to evaluate both the capacitive and the inductive coupling. The additivity of the coupling is shown and validated with several simulations

    High–Speed Data Transmission Subsystem of the SEOSAR/PAZ Satellite

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    This paper analyzes a digital interface and bus system modeling and optimization of the SEOSAR/PAZ Earth Observation satellite. The important part of the satellite is an X–band Synthetic Aperture Radar instrument that integrates 384 Transmit/Receive Modules located in 12 antenna panels 7.5 m away from the central processor and controlled by a synchronous 10 Mbps bidirectional serial protocol. This type of mid–range point–to–multipoint transmission is affected by bit errors due to crosstalk, transmission line attenuation and impedance mismatches. The high–speed data communication network has been designed to optimize the transmission by using a simulation model of the data distribution system which takes into account the worst–case scenario and by developing a lab–scaled prototype which exhibits BER of 10-11 for an interfering signal of 10 Vpp. The result is a point–to–multipoint bidirectional transmission network optimized in both directions with optimal values of loads and equalization resistors. This high–speed data transmission subsystem provides a compact design through a simple solution

    Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

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    This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 ”m CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator

    A Survey Addressing on High Performance On-Chip VLSI Interconnect

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    With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed

    Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

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    This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast
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