Gate-All-Around FETs: Nanowire and Nanosheet Structure

DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications

Heating Effects in Nanoscale Devices

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Compact modeling of the rf and noise behavior of multiple-gate mosfets

La reducción de la tecnología MOSFET planar ha sido la opción tecnológica dominante en las últimas décadas. Sin embargo, hemos llegado a un punto en el que los materiales y problemas en los dispositivos surgen, abriendo la puerta para estructuras alternativas de los dispositivos. Entre estas estructuras se encuentran los dispositivos DG, SGT y Triple-Gate. Estas tres estructuras están estudiadas en esta tesis, en el contexto de rducir las dimensiones de los dispositivos a tamaños tales que los mecanismos cuánticos y efectos de calan coro deben tenerse n cuenta. Estos efectos vienen con una seria de desafíos desde el pun to de vista de modelación, unos de los más grandes siendo el tiempo y los recursos comprometidos para ejecutar las simulaciones. para resolver este problema, esta tesis propone modelos comlets analíticos y compactos para cada una de las geometrías, validos desde DC hasta el modo de operación en Rf para los nodos tecnológicos futuros. Dichos modelos se han extendido para analizar el ruido de alta frecuencia en estos diapositivos

Impact of phonon scattering in Si/GaAs/InGaAs nanowires and FinFets: a NEGF perspective

This paper reviews our previous theoretical studies and gives further insight into phonon scattering in 3D small nanotransistors using non-equilibrium Green function methodology. The focus is on very small gate-all-around nanowires with Si, GaAs or InGaAs cores. We have calculated phonon-limited mobility and transfer characteristics for a variety of cross-sections at low and high drain bias. The nanowire cross-sectional area is shown to have a significant impact on the phonon-limited mobility and on the current reduction. In a study of narrow Si nanowires we have examined the spatially resolved power dissipation and the validity of Joule’s law. Our results show that only a fraction of the power is dissipated inside the drain region even for a relatively large simulated length extension (approximately 30 nm). When considering large source regions in the simulation domain, at low gate bias, a slight cooling of the source is observed. We have also studied the impact of the real part of phonon scattering self-energy on a narrow nanowire transistor. This real part is usually neglected in nanotransistor simulation, whereas we compute its impact on current–voltage characteristic and mobility. At low gate bias, the imaginary part strongly underestimated the current and the mobility by 50 %. At high gate bias, the two mobilities are similar and the effect on the current is negligible

Effects of mole fraction variations and scaling on total variability in InGaAs MOSFETs

Variability is one of the major roadblocks for III-V semiconductors in nanoscale devices, according to the recent International Roadmap for Devices and Systems (IRDS). A particular concern is the detrimental effect of variability of threshold voltage due to channel compositional variations. In this paper, we investigate the impact of this variability source and the effects of scaling on the performance of Dual-Gate-Ultra-Thin-Body (DG-UTB) In0.53Ga0.47As MOSFETs. We model mole fraction variations in terms of the Indium content by taking into account the spatial inhomogeneity of the channel and the corresponding bandgap variations, analyzing the effects on threshold voltage variability. We thus define a variability source, i.e., Band Gap Fluctuation (BGF), and we compare the associated variability with the ones from other important sources, namely, Random Dopant Fluctuation (RDF), Work Function Fluctuation (WFF), Body- and Gate-Line Edge Roughness (B-LER and G-LER). We then define three corner cases for mole fraction variations to determine worst-case variability. Finally, the impact of scaling on variability is assessed by comparing results for two technology nodes on the linear and saturation threshold voltage, V-T,V-lin,V- V-T,V-sat, on-current, I-ON, leakage current, I-OFF, and linear and saturation sub-threshold slope, SS. We find that although scaling has no impact on BGF-induced V-T variability, it increases the total V-T, lin variability as well as that for I-ON and I-OFF