축차 비교형 아날로그-디지털 변환기의 성능 향상을 위한 기법에 대한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 김수환.This thesis is written about a performance enhancement technique for the successive-approximation-register analog-to-digital converter (SAR ADC). More specifically, it focuses on improving the resolution of the SAR ADC. The basic operation principles and the architecture of the conventional SAR ADC is examined. To gain insight on areas of improvement, a deeper look is taken at the building components of the SAR ADC. Design considerations of these components are discussed, along with the performance limiting factors in the resolution and bandwidth domains. Prior works which challenge these problems in order to improve the performance of the SAR ADC are presented. To design SAR ADCs, a high-level modeling is presented. This model includes various non-ideal effects that occur in the design and operation. Simulation examples are shown how the model is efficient and useful in the initial top-level designing of the SAR ADC. Then, the thesis proposes a technique that can enhance the resolution. The SAR ADC using integer-based capacitor digital-to-analog converter (CDAC) exploiting redundancy is presented. This technique improves the mismatch problem that arises with the widely used split-capacitor structure in the CDAC of the SAR ADC. Unlike prior works, there is no additional overhead of additional calibration circuits or reference voltages. A prototype SAR ADC which uses the integer-based CDAC exploiting redundancy is designed for automotive applications. Measurement results show a resolution level of 12 bits even without any form of calibration. Finally, the conclusion about the operation and effectiveness on the proposed technique is drawn.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 5 CHAPTER 2 CONVENTIONAL SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTERS 7 2.1 INTRODUCTION 7 2.2 OPERATION PRINCIPLE OF THE CONVENTIONAL SAR ADC 8 2.2.1. OVERVIEW OF THE OPERATION 8 2.2.2. SAMPLING PHASE 10 2.2.3. CONVERSION PHASE 11 2.3 STRUCTURE OF THE CONVENTIONAL SAR ADC 15 2.3.1. FULL STRUCTURE OF THE CONVENTIONAL SAR ADC 15 2.3.2. CAPACITOR DIGITAL-TO-ANALOG CONVERTER (CDAC) 17 2.3.3. COMPARATOR 21 2.3.4. CONTROL LOGIC 23 2.4 PERFORMANCE LIMITING FACTORS 24 2.4.1. RESOLUTION LIMITING FACTORS 24 2.4.2. OPERATION BANDWIDTH LIMITING FACTORS 28 2.5 PRIOR WORK 30 2.5.1. INTRODUCTION 30 2.5.2. SPLIT-CAPACITOR STRUCTURE OF THE CDAC 31 2.5.3. REDUNDANCY AND CDAC WEIGHT DISTRIBUTION 33 2.5.4. ASYNCHRONOUS CONTROL LOGIC 36 2.5.5. CALIBRATION TECHNIQUES 37 2.5.4. DOUBLE-SAMPLING TECHNIQUE FOR SAMPLING TIME REDUCTION 38 2.5.6. TWO-COMPARATOR ARCHITECTURE FOR COMPARATOR DECISION TIME REDUCTION 40 2.5.7. MAJORITY VOTING FOR RESOLUTION ENHANCEMENT 41 CHAPTER 3 MODELING OF THE SAR ADC 43 3.1 INTRODUCTION 43 3.2 WEIGHT DISTRIBUTION OF THE CAPACITOR DAC AND REDUNDANCY 44 3.3 SPLIT-CAPACITOR ARRAY TECHNIQUE 47 3.4 PARASITIC EFFECTS OF THE CAPACITOR DAC 48 3.5 MISMATCH MODEL OF THE CAPACITOR DAC 51 3.6 SETTLING ERROR OF THE DAC 53 3.7 COMPARATOR DECISION ERROR 58 3.8 DIGITAL ERROR CORRECTION 59 CHAPTER 4 SAR ADC WITH INTEGER-BASED SPLIT-CDAC EXPLOITING REDUNDANCY FOR AUTOMOTIVE APPLICATIONS 60 4.1 INTRODUCTION 60 4.2 MOTIVATION 61 4.3 PRIOR WORK ON RESOLVING THE SPLIT-CAPACITOR CDAC MISMATCH FOR THE SAR ADC 64 4.3.1. CONVENTIONAL SPLIT-CAPACITOR CDAC FOR THE SAR ADC 64 4.3.2. SPLITTING THE LAST STAGE OF THE LSB-SIDE OF THE CDAC 66 4.3.3. CALIBRATION OF THE NON-INTEGER MULTIPLE BRIDGE CAPACITOR 67 4.3.4. INTEGER-MULTIPLE BRIDGE CAPACITOR WITH LSB-SIDE CAPACITOR ARRAY CALIBRATION 68 4.3.5. OVERSIZED BRIDGE CAPACITOR WITH ADDITIONAL FRACTIONAL REFERENCE VOLTAGE 69 4.4 PROPOSED INTEGER-BASED CDAC EXPLOITING REDUNDANCY FOR THE SAR ADC 70 4.5 CIRCUIT DESIGN 72 4.5.1. PROPOSED INTEGER-BASED CDAC EXPLOITING REDUNDANCY FOR SAR ADC 72 4.5.2. COMPARATOR 74 4.5.3. CONTROL LOGIC 75 4.6 IMPLEMENTATION AND EXPERIMENTAL RESULTS 76 4.6.1. LAYOUT 76 4.6.2. MEASUREMENT RESULTS AND CONCLUSIONS 82 CHAPTER 5 CONCLUSION AND FUTURE WORK 86 5.1 CONCLUSION 86 5.2 FUTURE WORK 87 APPENDIX. SAR ADC USING THRESHOLD-CONFIGURING COMPARATOR FOR ULTRASOUND IMAGING SYSTEMS 89 BIBLIOGRAPHY 120Docto

Applying the Split-ADC Architecture to a 16 bit, 1 MS/s differential Successive Approximation Analog-to-Digital Converter

Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CAL-DAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This thesis applies the“Split-ADC architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This thesis focuses on the specific implementation of the“Split-ADC self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC. The ADC can be calibrated with 105 conversions. This represents an improvement of 3 orders of magnitude over existing statistically-based calibration algorithms. Simulation results show that the linearity of the calibrated ADC improves to within ±1 LSB

캐패시터 미스매치 분석에 기반한 12-bit 1 MSps SAR ADC 설계

학위논문 (석사)-- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2019. 2. 김수환.본 논문에서는 캐패시터 미스매치가 successive approximation register (SAR) analog-to-digital converter (ADC)에 미치는 영향을 분석하고 이를 기반으로 설계한 캐패시터 digital-to-analog converter (DAC)으로 구현된 SAR ADC를 제안한다. 캐패시터 미스매치는 캐패시터 면적의 제곱근에 반비례한다. 따라서 캐패시터 미스매치를 줄이기 위해서는 캐패시터 면적을 늘려야하고 이는 전력 소모를 증가시킨다. 이 때문에 캐패시터 DAC의 크기를 결정하는 것은 SAR ADC의 설계에 있어 매우 중요하며 분석을 통해 최적화된 값을 찾는 것이 중요하다. 본 논문에서는 캐패시터 DAC의 각 캐패시터들의 미스매치로 인한 differential non-linearity (DNL)이 보다 작아지는 최소 캐패시터의 크기를 계산하였으며 이를 기반으로 스플릿 캐패시터 DAC과 더블 스플릿 캐패시터 DAC의 미스매치를 분석하였다. 본 논문은 미스매치 분석을 기반으로 미스매치 성능이 좋지 않은 캐패시터들의 크기를 키워 최적화한 캐패시터 DAC을 제안한다. 브릿지 캐패시터로 인한 선형성 저하를 막기 위해 브릿지 캐패시터 calibration 회로를 추가하였으며, 제안된 캐패시터 DAC의 성능이 기존의 스플릿 캐패시터 DAC의 성능과 비교하였을 때, 향상되었음을 monte carlo 모의실험 결과를 통해 증명하였다. 제안된 1MHz 12-bit SAR ADC 회로는 0.18 µm CMOS 공정에서 구현되었으며, 기준 전압을 내부에서 직접 생성하였다. Nyquist 입력을 주입하였을 때, 11.31 effective number of bits (ENOB)의 결과를 모의실험을 통해 얻었으며 4.6 V의 아날로그 공급 전압과 1.8 V의 디지털 공급전압에서 1.14 mW의 전력을 소모한다.This paper analyzes the impact of capacitor mismatch on successive approximation register analog-to-digital converter and proposes SAR ADC with capacitor digital-to-analog converter based on analysis of capacitor mismatch. The capacitor mismatch is inversely proportional to the square root of the capacitor area. In order to reduce the capacitor mismatch, the capacitor area must be increased, which increases the power consumption. Therefore, determining the size of the capacitor DAC is very important for the SAR ADC design and it is important to find the optimized value through analysis. This paper calculates the minimum capacitor size that the DNL due to the mismatch of each capacitor in the capacitor DAC is less than . Based on mismatch calculation, this paper analyzes the mismatch of both the split capacitor DAC and the double split capacitor DAC. This paper proposes an optimized capacitor DAC based on mismatch analysis by improving the size of capacitors with poor mismatch performance. A bridge capacitor calibration circuit was added to prevent linearity degradation due to the bridge capacitor. Montecarlo simulation results show that the performance of the proposed capacitor DAC is improved when compared with that of the conventional split capacitor DAC. The proposed 1 MHz 12-bit SAR ADC circuit is implemented in a 0.18 µm CMOS process and the reference voltage is directly generated internally. When the Nyquist input is injected, the result of 11.31 ENOB is obtained through simulation and consumes 1.14 mW of power at an analog supply voltage of 4.6 V and a digital supply voltage of 1.8 V.제 1 장 서 론 1 제 1 절 연구의 배경 1 제 2 절 기본적인 SAR ADC의 동작 원리 4 제 2 장 캐패시터 DAC 8 제 1 절 캐패시터 DAC의 design issues 8 1. kT/C 잡음 8 2. 안정화 시간 10 3. 캐패시터 미스매치 11 제 2 절 스플릿 캐패시터 DAC 13 제 3 절 브릿지 캐패시터 미스매치 calibration 기법 16 1. 브릿지 캐패시터 미스매치 calibration 기법의 원리 16 2. 브릿지 캐패시터 미스매치 calibration 기법의 동작 설명 21 제 3 장 제안하는 캐패시터 DAC을 이용한 SAR ADC의 설계 24 제 1 절 캐패시터 DAC 미스매치 분석 24 1. 캐패시터 미스매치 계산 24 2. 스플릿 캐패시터 DAC의 미스매치 분석 26 3. 더블 스플릿 캐패시터 DAC의 미스매치 분석 27 제 2 절 제안하는 캐패시터 DAC 29 제 3 절 SAR ADC의 구현 31 제 4 장 Layout 및 모의실험 결과 36 제 1 절 Layout 36 제 2 절 모의실험 결과 37 제 5 장 결 론 43 참고문헌 44 Abstract 45Maste

High-Resolution ADCs Design in Image Sensors

This paper presents design considerations for high-resolution and high-linearity ADCs for biomedical imaging ap-plications. The work discusses how to improve dynamic spec-ifications such as Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) in ultra-low power and high-resolution analog-to-digital converters (ADCs) including successive approximation register (SAR) for biomedical imaging application. The results show that with broad range of mismatch error, the SFDR is enhanced by about 10 dB with the proposed performance enhancement technique, which makes it suitable for high resolution image sensors sensing systems

Exploiting smallest error to calibrate non-linearity in SAR ADCs

This paper presents a statistics-optimised organisation technique to achieve better element matching in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in smart sensor systems. We demonstrate the proposed technique ability to achieve a significant improvement of around 23 dB on Spurious Free Dynamic Range (SFDR) of the ADC than the conventional, testing with a capacitor mismatch σu = 0.2% in a 14 bit SAR ADC system. For the static performance, the max root mean square (rms) value of differential nonlinearity (DNL) reduces from 1.63 to 0.20 LSB and the max rms value of integral nonlinearity (INL) reduces from 2.10 to 0.21 LSB. In addition, it is demonstrated that by applying grouping optimisation and strategy optimisation, the performance boosting on SFDR can be effectively achieved. Such great improvement on the resolution of the ADC only requires an off-line pre-processing digital part

High Linearity SAR ADC for Smart Sensor Applications

This paper presents capacitive array optimization technique to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor application. Monte Carlo simulation results show that capacitive array optimization technique proposed can make the SFDR, SNDR and (Signal-to-Noise Ratio) SNR more concentrated, which means the differences between maximum value and minimum value of SFDR, SNDR and SNR are much smaller than the conventional calibration techniques, more stable performance enhancement can be achieved, and the averaged SFDR is improved from 72.9 dB to 91.1 dB by using the capacitive array optimization method, 18.2 dB improvement of SFDR is obtained with only little expense of digital logic circuits, which makes it good choice for high resolution and high linearity smart sensing systems

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration

A 12-bit 50MS/s SAR ADC implemented in 65nm CMOS technology is presented. The design employs redundancy to relax the DAC settling requirement and to provide sufficient room for errors such that the static nonlinearity caused by capacitor mismatches can be digitally removed. The redundancy is incorporated into the design using a tri-level switching scheme and our modified split-capacitor array to achieve the highest switching efficiency while still preserving the symmetry in error tolerance. A new code-density based digital background calibration algorithm that requires no special calibration signals or additional analog hardware is also developed. The calibration is performed by using the input signal as stimulus and the effectiveness is verified both in simulation and through measured data. The prototype achieves a 67.4dB SNDR at 50MS/s, while dissipating 2.1mW from a 1.2V supply, leading to FoM of 21.9fJ/conv.-step at Nyquist frequency.MIT Masdar Progra