A Discrete-Time Technique for Linearity Enhancement of Wideband Receivers

A new signal processing technique is introduced to enhance the linearity performance of wideband radio frequency (RF) receivers. The proposed technique combines the advancements in mixer first architectures with a library of binary sequences as local oscillator signals to enable wide instantaneous bandwidth and high linearity for the RF receiver. To do so, N-bit pseudo-random-binary-sequences (PRBS) are used as local oscillator signals. The RF input signal is multiplied with the PRBS at the mixer and then averaged over the full sequence. This in effect reduces the amplitude of the signal and improves the overall linearity of the system. In order to enable full reconstruction of the input signal N channels are used with each employing a shifted version of a PRBS. The effect of the proposed technique on different aspects of the system performance such as noise and linearity is discussed. In addition, the effect of nonidealities stemming from hardware implementation on the overall performance are studied. A prototype integrated circuit (IC) is implemented in 130\,nm CMOS technology to demonstrate the feasibility of the proposed technique. The design procedure of each circuit block is described and simulation results are used to evaluate the performance. The device is fabricated and characterized using a custom data acquisition system. Measurement results show good agreement with the expected values from simulation and analytical analysis. Calibration techniques are introduced to minimize the effect of DC offsets, gain mismatches, and timing skews. Modifications to the implemented CMOS circuit are proposed to enable such calibrations and further enhance the overall performance of the system. The requirements for the precision of calibration techniques are derived and used to find the specifications of circuit block that are designed to enable these techniques. Calibration of DC offsets along with gain mismatches is carried out for the fabricated IC and results are shown. A digitally assisted technique is proposed to enable the calibration of timing skews. In addition, a review of additional implementation shortcomings that can affect the system performance are reviewed. Finally, a conclusion of the dissertation is presented along with potential future work for further enhancement of the system performance

Estimation and Calibration Algorithms for Distributed Sampling Systems

Thesis Supervisor: Gregory W. Wornell Title: Professor of Electrical Engineering and Computer ScienceTraditionally, the sampling of a signal is performed using a single component such as an analog-to-digital converter. However, many new technologies are motivating the use of multiple sampling components to capture a signal. In some cases such as sensor networks, multiple components are naturally found in the physical layout; while in other cases like time-interleaved analog-to-digital converters, additional components are added to increase the sampling rate. Although distributing the sampling load across multiple channels can provide large benefits in terms of speed, power, and resolution, a variety mismatch errors arise that require calibration in order to prevent a degradation in system performance. In this thesis, we develop low-complexity, blind algorithms for the calibration of distributed sampling systems. In particular, we focus on recovery from timing skews that cause deviations from uniform timing. Methods for bandlimited input reconstruction from nonuniform recurrent samples are presented for both the small-mismatch and the low-SNR domains. Alternate iterative reconstruction methods are developed to give insight into the geometry of the problem. From these reconstruction methods, we develop time-skew estimation algorithms that have high performance and low complexity even for large numbers of components. We also extend these algorithms to compensate for gain mismatch between sampling components. To understand the feasibility of implementation, analysis is also presented for a sequential implementation of the estimation algorithm. In distributed sampling systems, the minimum input reconstruction error is dependent upon the number of sampling components as well as the sample times of the components. We develop bounds on the expected reconstruction error when the time-skews are distributed uniformly. Performance is compared to systems where input measurements are made via projections onto random bases, an alternative to the sinc basis of time-domain sampling. From these results, we provide a framework on which to compare the effectiveness of any calibration algorithm. Finally, we address the topic of extreme oversampling, which pertains to systems with large amounts of oversampling due to redundant sampling components. Calibration algorithms are developed for ordering the components and for estimating the input from ordered components. The algorithms exploit the extra samples in the system to increase estimation performance and decrease computational complexity

Post Conversion Correction of Non-Linear Mismatches for Time Interleaved Analog-to-Digital Converters

Time Interleaved Analog-to-Digital Converters (TI-ADCs) utilize an architecture which enables conversion rates well beyond the capabilities of a single converter while preserving most or all of the other performance characteristics of the converters on which said architecture is based. Most of the approaches discussed here are independent of architecture; some solutions take advantage of specific architectures. Chapter 1 provides the problem formulation and reviews the errors found in ADCs as well as a brief literature review of available TI-ADC error correction solutions. Chapter 2 presents the methods and materials used in implementation as well as extend the state of the art for post conversion correction. Chapter 3 presents the simulation results of this work and Chapter 4 concludes the work. The contribution of this research is three fold: A new behavioral model was developed in SimulinkTM and MATLABTM to model and test linear and nonlinear mismatch errors emulating the performance data of actual converters. The details of this model are presented as well as the results of cumulant statistical calculations of the mismatch errors which is followed by the detailed explanation and performance evaluation of the extension developed in this research effort. Leading post conversion correction methods are presented and an extension with derivations is presented. It is shown that the data converter subsystem architecture developed is capable of realizing better performance of those currently reported in the literature while having a more efficient implementation