Affordable techniques for dependable microprocessor design

As high computing power is available at an affordable cost, we rely on microprocessor-based systems for much greater variety of applications. This dependence indicates that a processor failure could have more diverse impacts on our daily lives. Therefore, dependability is becoming an increasingly important quality measure of microprocessors.;Temporary hardware malfunctions caused by unstable environmental conditions can lead the processor to an incorrect state. This is referred to as a transient error or soft error. Studies have shown that soft errors are the major source of system failures. This dissertation characterizes the soft error behavior on microprocessors and presents new microarchitectural approaches that can realize high dependability with low overhead.;Our fault injection studies using RISC processors have demonstrated that different functional blocks of the processor have distinct susceptibilities to soft errors. The error susceptibility information must be reflected in devising fault tolerance schemes for cost-sensitive applications. Considering the common use of on-chip caches in modern processors, we investigated area-efficient protection schemes for memory arrays. The idea of caching redundant information was exploited to optimize resource utilization for increased dependability. We also developed a mechanism to verify the integrity of data transfer from lower level memories to the primary caches. The results of this study show that by exploiting bus idle cycles and the information redundancy, an almost complete check for the initial memory data transfer is possible without incurring a performance penalty.;For protecting the processor\u27s control logic, which usually remains unprotected, we propose a low-cost reliability enhancement strategy. We classified control logic signals into static and dynamic control depending on their changeability, and applied various techniques including commit-time checking, signature caching, component-level duplication, and control flow monitoring. Our schemes can achieve more than 99% coverage with a very small hardware addition. Finally, a virtual duplex architecture for superscalar processors is presented. In this system-level approach, the processor pipeline is backed up by a partially replicated pipeline. The replication-based checker minimizes the design and verification overheads. For a large-scale superscalar processor, the proposed architecture can bring 61.4% reduction in die area while sustaining the maximum performance

AUTOMATED NETWORK FAULT INFERENCE TOOL (AN FIT)

The lack of specialized experts in diagnosing network faults, inconsistencies of diagnose results and professional opinions, time-consuming and growing complexity of this task; has motivated the dewlopment of our c\utomated Network Fault Diagnostic System. This system aims to serve as an intelligent diai-,'llOStic system that will be able to produce fast, accurate, user-friendly and appropriate suggestions that will assist normal network users and administrators respectively. To ensure the realistic and successful development of the system, we adopt Extreme Programming methodology. l\lany efforts have been paid to implement a novel and efficient solution to precisely diagnose problems and in timely manner. The methodology has e\·oh-ed from rule-based systems through case-based systems to more recent model-based systems. Our project is designed upon case-based diagnostic approach as it suggests the use of previously experienced, concrete problem or cases instead of rules or modelling yueries evaluation. We propose a system that will provide reactive response on-demand in term of error messages based on inaccessible URL input entered by user. 'I he system will then diagnose the problems based on the formulated inference table that is comprised of pre-defined failure cases and test cases which will be developed via user-defined functions and general network probing tools. hom there, we expect the output to be returned in command line error mess;tges. To measure the success of the system, four Key Performance Indicators (KPI) hm-e been identified as evaluation metrics which are cm·erage, accuracy, time and response. Hence, unit testing, integration testing and usability test will be conducted to obtain the assessment results. We claim that the system could initiate an extensible framework for network services that act as a community support tooL However, at present we narrow down our focus on Web Set\~ce application but by all means encouraging and welcoming the extension to other network services or adding in new test cases as future development for the benefit of all network users

Efficient Control Message Dissemination in Dense Wireless Lighting Networks

Modern lighting systems using LED light sources lead to dense lighting installations. The control of such systems using wireless Machine-to-Machine (M2M) where standard LED light sources are replaced by wirelessly controllable LED light sources create new problems which are investigated in this thesis. Current approaches for control message transmission is such networks are based on broadcasting messages among luminaires. However, adequate communication performance - in particular, sufficiently low latency and synchronicity - is difficult to ensure in such networks, in particular, if the network is part of a wireless building management system and carries not only low-latency broadcast messages but also collects data from sensors. In this thesis, the problem of simultaneously controlling dense wireless lighting control networks with a higher number of luminaires is addressed. Extensive computer simulation shows that current state-of-the-art protocols are not suitable for lighting control applications, especially if complex applications are required such as dimming or colour tuning. The novel D³LC-Suite is proposed, which is specially designed for dense wireless lighting control networks. This suite includes three sub-protocols. First, a protocol to organize a network in form of a cluster tree named CIDER. To ensure that intra-cluster messages can be exchanged simultaneously, a weighted colouring algorithm is applied to reduce the inter cluster interference. To disseminate efficiently control messages a protocol is proposed named RLL. The D³LC-Suite is evaluated and validated using different methods. A convergence analysis show that CIDER is able to form a network in a matter of minutes. Simulation results of RLL indicate that this protocol is well suited for dense wireless applications. In extensive experiments, it is shown that the D³LC-Suite advances the current state-of-the-art in several aspects. The suite is able to deliver control messages across multiple hops meeting the requirements of lighting applications. Especially, it provides a deterministic latency, very promising packet loss ratios in low interference environments, and mechanisms for simultaneous message delivery which is important in terms of Quality of Experience (QoE

Gollach : configuration of a cluster based linux virtual server

Includes bibliographical references.This thesis describes the Gollach cluster. The Gollach is an eight machine computing cluster that is aimed at being a general purpose computing resource for research purposes. This includes image processing and simulations. The main quest in this project is to create a cluster server that gives increased computational power and a unified system image (at several levels) without requiring the users to learn specialised tricks. At the same time the cluster must not be tasking to administer

Sixth Goddard Conference on Mass Storage Systems and Technologies Held in Cooperation with the Fifteenth IEEE Symposium on Mass Storage Systems

This document contains copies of those technical papers received in time for publication prior to the Sixth Goddard Conference on Mass Storage Systems and Technologies which is being held in cooperation with the Fifteenth IEEE Symposium on Mass Storage Systems at the University of Maryland-University College Inn and Conference Center March 23-26, 1998. As one of an ongoing series, this Conference continues to provide a forum for discussion of issues relevant to the management of large volumes of data. The Conference encourages all interested organizations to discuss long term mass storage requirements and experiences in fielding solutions. Emphasis is on current and future practical solutions addressing issues in data management, storage systems and media, data acquisition, long term retention of data, and data distribution. This year's discussion topics include architecture, tape optimization, new technology, performance, standards, site reports, vendor solutions. Tutorials will be available on shared file systems, file system backups, data mining, and the dynamics of obsolescence

A SPARQL query engine over Web ontologies using contextual logic programming

Na World Wide Web os programas informáticos conseguem processar facilmente a estrutura das páginas. Contudo, são necessárias técnicas avançadas para determinar o conteúdo semântico dessas páginas. A Semantic Web é uma extensão da Web que tenta ultrapassar esta dificuldade. Criar anotações nas páginas com informação acerca do seu conteúdo, descrita. Numa linguagem formal, ajuda o processamento automatizado da semântica da página. A integração dessa informação semântica, que pode ser descrita através de OWL, com uma. framework de Programação em Logica Contextual disponibiliza uma maneira clara e simples de representar e interrogar ontologias. As principais contribuições deste trabalho para esse objetivo são: - Um sistema capaz de representar ontologias OWL DL e de realizar interrogações baseadas nessa representação - Um médulo de resposta a interrogações SPARQL: permite disponibilizar o sistema a um elevado número de utilizadores e processes automáticos e possibilita anunciá-lo como um serviço Web. /ABSTRACT - In the World Wide Web a machine can easily process the structure of resources. However, more advanced techniques are necessary to determine the semantic contents of such resources. The Semantic Web is an enhancement of the Web which aims to overcome this difficulty. Annotating Web resources with information about their contents, described using a formal language, helps machines process the semantics of the resource. Integrating that semantic information, which can be described using OWL with a Contextual Logic Programming framework provides a clear and simple way to represent and query an ontology. The main contributions of this work to that purpose are: - A system capable of representing OWL DL ontologies and performing queries over that representation - A SPARQL query answering module: this makes the system available to a wide range of users and automated processes, enabling the possibility of advertising it as a web service

Fourth NASA Goddard Conference on Mass Storage Systems and Technologies

This report contains copies of all those technical papers received in time for publication just prior to the Fourth Goddard Conference on Mass Storage and Technologies, held March 28-30, 1995, at the University of Maryland, University College Conference Center, in College Park, Maryland. This series of conferences continues to serve as a unique medium for the exchange of information on topics relating to the ingestion and management of substantial amounts of data and the attendant problems involved. This year's discussion topics include new storage technology, stability of recorded media, performance studies, storage system solutions, the National Information infrastructure (Infobahn), the future for storage technology, and lessons learned from various projects. There also will be an update on the IEEE Mass Storage System Reference Model Version 5, on which the final vote was taken in July 1994

Design and verification of the rollback chip using HOP: a case study of formal methods applied to hardware design

technical reportThe use of formal methods in hardware design improves the quality of designs in many ways: it promotes better understanding of the design; it permits systematic design refinement through the discovery of invariants; and it allows design verification (informal or formal). In this paper we illustrate the use of formal methods in the design of a custom hardware system called the 'Rollback Chip' (RBC), conducted using a simple hardware design specification language called 'HOP'. An informal description of the requirements of the RBC is first given, followed by a behavioral description of RBC stating its desired behavior. The behavioral description is refined into progressively more efficient designs, terminating in a structural description. Key refinement steps are based on system invariants that are discovered during the design, and proved correct during design verification. The first step in design verification is to apply a program called PARCOMP to derive a behavioral description from the structural description of the RBC. The derived behavior is then compared against the desired behavior using equational verification techniques. This work demonstrates that formal methods can be fruitfully applied to a non-trivial hardware design. It also illustrates the particular advantages of our approach based on HOP and PARCOMP. Last, but not the least, it formally verifies the RBC mechanism itself