Improving the Performance and Energy Efficiency of GPGPU Computing through Adaptive Cache and Memory Management Techniques

Department of Computer Science and EngineeringAs the performance and energy efficiency requirement of GPGPUs have risen, memory management techniques of GPGPUs have improved to meet the requirements by employing hardware caches and utilizing heterogeneous memory. These techniques can improve GPGPUs by providing lower latency and higher bandwidth of the memory. However, these methods do not always guarantee improved performance and energy efficiency due to the small cache size and heterogeneity of the memory nodes. While prior works have proposed various techniques to address this issue, relatively little work has been done to investigate holistic support for memory management techniques. In this dissertation, we analyze performance pathologies and propose various techniques to improve memory management techniques. First, we investigate the effectiveness of advanced cache indexing (ACI) for high-performance and energy-efficient GPGPU computing. Specifically, we discuss the designs of various static and adaptive cache indexing schemes and present implementation for GPGPUs. We then quantify and analyze the effectiveness of the ACI schemes based on a cycle-accurate GPGPU simulator. Our quantitative evaluation shows that ACI schemes achieve significant performance and energy-efficiency gains over baseline conventional indexing scheme. We also analyze the performance sensitivity of ACI to key architectural parameters (i.e., capacity, associativity, and ICN bandwidth) and the cache indexing latency. We also demonstrate that ACI continues to achieve high performance in various settings. Second, we propose IACM, integrated adaptive cache management for high-performance and energy-efficient GPGPU computing. Based on the performance pathology analysis of GPGPUs, we integrate state-of-the-art adaptive cache management techniques (i.e., cache indexing, bypassing, and warp limiting) in a unified architectural framework to eliminate performance pathologies. Our quantitative evaluation demonstrates that IACM significantly improves the performance and energy efficiency of various GPGPU workloads over the baseline architecture (i.e., 98.1% and 61.9% on average, respectively) and achieves considerably higher performance than the state-of-the-art technique (i.e., 361.4% at maximum and 7.7% on average). Furthermore, IACM delivers significant performance and energy efficiency gains over the baseline GPGPU architecture even when enhanced with advanced architectural technologies (e.g., higher capacity, associativity). Third, we propose bandwidth- and latency-aware page placement (BLPP) for GPGPUs with heterogeneous memory. BLPP analyzes the characteristics of a application and determines the optimal page allocation ratio between the GPU and CPU memory. Based on the optimal page allocation ratio, BLPP dynamically allocate pages across the heterogeneous memory nodes. Our experimental results show that BLPP considerably outperforms the baseline and state-of-the-art technique (i.e., 13.4% and 16.7%) and performs similar to the static-best version (i.e., 1.2% difference), which requires extensive offline profiling.clos

The ZCache: Decoupling Ways and Associativity

Abstract—The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically im-proved by increasing the number of ways. This reduces conflict misses, but increases hit latency and energy, placing a stringent trade-off on cache design. We present the zcache, a cache design that allows much higher associativity than the number of physical ways (e.g. a 64-associative cache with 4 ways). The zcache draws on previous research on skew-associative caches and cuckoo hashing. Hits, the common case, require a single lookup, incurring the latency and energy costs of a cache with a very low number of ways. On a miss, additional tag lookups happen off the critical path, yielding an arbitrarily large number of replacement candidates for the incoming block. Unlike conventional designs, the zcache provides associativity by increasing the number of replacement candidates, but not the number of cache ways. To understand the implications of this approach, we develop a general analysis framework that allows to compare associativity across different cache designs (e.g. a set-associative cache and a zcache) by representing associativity as a probability distribution. We use this framework to show that for zcaches, associativity depends only on the number of replacement candidates, and is independent of other factors (such as the number of cache ways or the workload). We also show that, for the same number of replacement candidates, the associativity of a zcache is superior than that of a set-associative cache for most workloads. Finally, we perform detailed simulations of multithreaded and multiprogrammed workloads on a large-scale CMP with zcache as the last-level cache. We show that zcaches provide higher performance and better energy efficiency than conventional caches without incurring the overheads of designs with a large number of ways. I

Spectral and Energy Efficiency Maximization for Content-Centric C-RANs with Edge Caching

This paper aims to maximize the spectral and energy efficiencies of a content-centric cloud radio access network (C-RAN), where users requesting the same contents are grouped together. Data are transferred from a central baseband unit to multiple remote radio heads (RRHs) equipped with local caches. The RRHs then send the received data to each group's user. Both multicast and unicast schemes are considered for data transmission. We formulate mixed-integer nonlinear problems in which user association, RRH activation, data rate allocation, and signal precoding are jointly designed. These challenging problems are subject to minimum data rate requirements, limited fronthaul capacity, and maximum RRH transmit power. Employing successive convex quadratic programming, we propose iterative algorithms with guaranteed convergence to Fritz John solutions. Numerical results confirm that the proposed joint designs markedly improve the spectral and energy efficiencies of the considered content-centric C-RAN compared to benchmark schemes. Importantly, they show that unicasting outperforms multicasting in terms of spectral efficiency in both cache and cache-less scenarios. In terms of energy efficiency, multicasting is the best choice for the system without cache whereas unicasting is best for the system with cache. Finally, edge caching is shown to improve both spectral and energy efficiencies.This work is supported in part by an ECRHDR scholarship from The University of Newcastle, in part by the Australian Research Council Discovery Project grants DP170100939 and DP160101537

A New Look at Physical Layer Security, Caching, and Wireless Energy Harvesting for Heterogeneous Ultra-dense Networks

Heterogeneous ultra-dense networks enable ultra-high data rates and ultra-low latency through the use of dense sub-6 GHz and millimeter wave (mmWave) small cells with different antenna configurations. Existing work has widely studied spectral and energy efficiency in such networks and shown that high spectral and energy efficiency can be achieved. This article investigates the benefits of heterogeneous ultra-dense network architecture from the perspectives of three promising technologies, i.e., physical layer security, caching, and wireless energy harvesting, and provides enthusiastic outlook towards application of these technologies in heterogeneous ultra-dense networks. Based on the rationale of each technology, opportunities and challenges are identified to advance the research in this emerging network.Comment: Accepted to appear in IEEE Communications Magazin

Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime

Near-Threshold Computing embodies an intriguing choice for mobile processors due to the promise of superior energy efficiency, extending the battery life of these devices while reducing the peak power draw. However, process, voltage, and temperature variations cause a significantly high failure rate of Level One cache cells in the near-threshold regime a stark contrast to designs in the super-threshold regime, where fault sites are rare. This thesis work shows that faulty cells in the near-threshold regime are highly clustered in certain regions of the cache. In addition, popular mobile benchmarks are studied to investigate the impact of run-time workloads on timing faults manifestation. A technique to mitigate the run-time faults is proposed. This scheme maps frequently used data to healthy cache regions by exploiting the application cache behaviors. The results show up to 78% gain in performance over two other state-of-the-art techniques