Minicomputer Concepts

This thesis presents a study of concepts used in the design of minicomputers currently on the market. The material is drawn from research on sixteen minicomputer systems.Computing and Information Science

Talus: A simple way to remove cliffs in cache performance

Caches often suffer from performance cliffs: minor changes in program behavior or available cache space cause large changes in miss rate. Cliffs hurt performance and complicate cache management. We present Talus, a simple scheme that removes these cliffs. Talus works by dividing a single application's access stream into two partitions, unlike prior work that partitions among competing applications. By controlling the sizes of these partitions, Talus ensures that as an application is given more cache space, its miss rate decreases in a convex fashion. We prove that Talus removes performance cliffs, and evaluate it through extensive simulation. Talus adds negligible overheads, improves single-application performance, simplifies partitioning algorithms, and makes cache partitioning more effective and fair.National Science Foundation (U.S.) (Grant CCF-1318384

A NASA family of minicomputer systems, Appendix A

This investigation was undertaken to establish sufficient specifications, or standards, for minicomputer hardware and software to provide NASA with realizable economics in quantity purchases, interchangeability of minicomputers, software, storage and peripherals, and a uniformly high quality. The standards will define minicomputer system component types, each specialized to its intended NASA application, in as many levels of capacity as required

Hardware and Software Considerations for Improving the Throughput of Scientific Computation Computers

In this paper, hardware and software techniques are presented for improving the Throughput (defined as computations per dollar) of computing systems which are oriented towards high-precision floating point computations. The various improvements are referenced to a baseline of the PDP 11/20, the NOVA 1200, and the TI 960A, all 16 bit minicomputers. The most beneficial hardware improvement is the inclusion of a Floating Point Processor, which yields up to 200X Throughput increase over a software floating point package. The inclusion of a cache high speed local memory and the availability of Polish Notation format instructions are shown to provide less than a 5X increase each. The use of 48 bit data paths, numerous registers devoted to various processor functions, instruction look ahead, a system I/O controller which frees the processor from I/O work, and partitioned main memory, result in a combined Throughput increase of 5.9X

Instruction prefetch strategies in a pipelined processor

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1983.MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERINGIncludes bibliographical references.by Hubert Rae McLellan, Jr.M.S

Study of Virtual Memory

This research report gives a general description of virtual memory systems. The mechanisms and policies and their effect on the operation and efficiency of virtual memory are explained. A virtual memory using a real time virtual address decoder, to decode a 32 bits of virtual address for the secondary memory to obtain the primary address location discussed. The decoder is developed with the use of associative or content-addressable memories. Replacement algorithms, used for selecting the pages of the main memory to be replaced, are described. The hardware implementation of the least recently used and least often used replacement policies using associative memories is presented