An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics

Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of the analytics pipeline. Using encryption to protect sensitive data at the boundary of the on-chip analytics engine is a way to address data security issues. To cope with the combined workload of analytics and encryption in a tight power envelope, we propose Fulmine, a System-on-Chip based on a tightly-coupled multi-core cluster augmented with specialized blocks for compute-intensive data processing and encryption functions, supporting software programmability for regular computing tasks. The Fulmine SoC, fabricated in 65nm technology, consumes less than 20mW on average at 0.8V achieving an efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to 25MIPS/mW in software. As a strong argument for real-life flexible application of our platform, we show experimental results for three secure analytics use cases: secure autonomous aerial surveillance with a state-of-the-art deep CNN consuming 3.16pJ per equivalent RISC op; local CNN-based face detection with secured remote recognition in 5.74pJ/op; and seizure detection with encrypted data collection from EEG within 12.7pJ/op.Comment: 15 pages, 12 figures, accepted for publication to the IEEE Transactions on Circuits and Systems - I: Regular Paper

06141 Abstracts Collection -- Dynamically Reconfigurable Architectures

From 02.04.06 to 07.04.06, the Dagstuhl Seminar 06141 ``Dynamically Reconfigurable Architectures\u27\u27 was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research, and ongoing work and open problems were discussed. Abstracts of the presentations given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full papers are provided, if available

Design Solutions For Modular Satellite Architectures

The cost-effective access to space envisaged by ESA would open a wide range of new opportunities and markets, but is still many years ahead. There is still a lack of devices, circuits, systems which make possible to develop satellites, ground stations and related services at costs compatible with the budget of academic institutions and small and medium enterprises (SMEs). As soon as the development time and cost of small satellites will fall below a certain threshold (e.g. 100,000 to 500,000 €), appropriate business models will likely develop to ensure a cost-effective and pervasive access to space, and related infrastructures and services. These considerations spurred the activity described in this paper, which is aimed at: - proving the feasibility of low-cost satellites using COTS (Commercial Off The Shelf) devices. This is a new trend in the space industry, which is not yet fully exploited due to the belief that COTS devices are not reliable enough for this kind of applications; - developing a flight model of a flexible and reliable nano-satellite with less than 25,000€; - training students in the field of avionics space systems: the design here described is developed by a team including undergraduate students working towards their graduation work. The educational aspects include the development of specific new university courses; - developing expertise in the field of low-cost avionic systems, both internally (university staff) and externally (graduated students will bring their expertise in their future work activity); - gather and cluster expertise and resources available inside the university around a common high-tech project; - creating a working group composed of both University and SMEs devoted to the application of commercially available technology to space environment. The first step in this direction was the development of a small low cost nano-satellite, started in the year 2004: the name of this project was PiCPoT (Piccolo Cubo del Politecnico di Torino, Small Cube of Politecnico di Torino). The project was carried out by some departments of the Politecnico, in particular Electronics and Aerospace. The main goal of the project was to evaluate the feasibility of using COTS components in a space project in order to greatly reduce costs; the design exploited internal subsystems modularity to allow reuse and further cost reduction for future missions. Starting from the PiCPoT experience, in 2006 we began a new project called ARaMiS (Speretta et al., 2007) which is the Italian acronym for Modular Architecture for Satellites. This work describes how the architecture of the ARaMiS satellite has been obtained from the lesson learned from our former experience. Moreover we describe satellite operations, giving some details of the major subsystems. This work is composed of two parts. The first one describes the design methodology, solutions and techniques that we used to develop the PiCPoT satellite; it gives an overview of its operations, with some details of the major subsystems. Details on the specifications can also be found in (Del Corso et al., 2007; Passerone et al, 2008). The second part, indeed exploits the experience achieved during the PiCPoT development and describes a proposal for a low-cost modular architecture for satellite

Low Power IoT based Automated Manhole Cover Monitoring System as a Smart City application

With the increased population in the big cities, Internet of Things (IoT) devices to be used as automated monitoring systems are required in many of the Smart city’s applications. Monitoring road infrastructure such as a manhole cover (MC) is one of these applications. Automating monitoring manhole cover structure has become more demanding, especially when the number of MC failure increases rapidly: it affects the safety, security and the economy of the society. Only 30% of the current MC monitoring systems are automated with short lifetime in comparison to the lifetime of the MC, without monitoring all the MC issues and without discussing the challenges of the design from IoT device design point of view. Extending the lifetime of a fully automated IoT-based MC monitoring system from circuit design point of view was studied and addressed in this research. The main circuit that consumes more power in the IoT-based MC monitoring system is the analogue to digital converter (ADC) found at the data acquisition module (DAQ). In several applications, the compressive sensing (CS) technique proved its capability to reduce the power consumption for ADC. In this research, CS has been investigated and studied deeply to reach the aim of the research. CS based ADC is named analogue to information converter (AIC). Because the heart of the AIC is the pseudorandom number generator (PRNG), several researchers have used it as a key to secure the data, which makes AIC more suitable for IoT device design. Most of these PRNG designs for AIC are hardware implemented in the digital circuit design. The presence of digital PRNG at the AIC analogue front end requires: a) isolating digital and analogue parts, and b) using two different power supplies and grounds for analogue and digital parts. On the other hand, analogue circuit design becomes more demanding for the sake of the power consumption, especially after merging the analogue circuit design with other fields such as neural networks and neuroscience. This has motivated the researcher to propose two low-power analogue chaotic oscillators to replace digital PRNG using opamp Schmitt Trigger. The proposed systems are based on a coupling oscillator concept. The design of the proposed systems is based on: First, two new modifications for the well-known astable multivibrator using opamp Schmitt trigger. Second, the waveshaping design technique is presented to design analogue chaotic oscillators instead of starting with complex differential equations as it is the case for most of the chaotic oscillator designs. This technique helps to find easy steps and understanding of building analogue chaotic oscillators for electronic circuit designers. The proposed systems used off the shelf components as a proof of concept. The proposed systems were validated based on: a) the range of the temperature found beneath a manhole cover, and b) the signal reconstruction under the presence and the absence of noise. The results show decent performance of the proposed system from the power consumption point of view, as it can exceed the lifetime of similar two opamps based Jerk chaotic oscillators by almost one year for long lifetime applications such as monitoring MC using Li-Ion battery. Furthermore, in comparison to PRNG output sequence generated by a software algorithm used in AIC framework in the presence of the noise, the first proposed system output sequence improved the signal reconstruction by 6.94%, while the second system improved the signal reconstruction by 17.83

Cryptoraptor : high throughput reconfigurable cryptographic processor for symmetric key encryption and cryptographic hash functions

textIn cryptographic processor design, the selection of functional primitives and connection structures between these primitives are extremely crucial to maximize throughput and flexibility. Hence, detailed analysis on the specifications and requirements of existing crypto-systems plays a crucial role in cryptographic processor design. This thesis provides the most comprehensive literature review that we are aware of on the widest range of existing cryptographic algorithms, their specifications, requirements, and hardware structures. In the light of this analysis, it also describes a high performance, low power, and highly flexible cryptographic processor, Cryptoraptor, that is designed to support both today's and tomorrow's encryption standards. To the best of our knowledge, the proposed cryptographic processor supports the widest range of cryptographic algorithms compared to other solutions in the literature and is the only crypto-specific processor targeting the future standards as well. Unlike previous work, we aim for maximum throughput for all known encryption standards, and to support future standards as well. Our 1GHz design achieves a peak throughput of 128Gbps for AES-128 which is competitive with ASIC designs and has 25X and 160X higher throughput per area than CPU and GPU solutions, respectively.Electrical and Computer Engineerin