Reducing branch delay to zero in pipelined processors

A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution of branches. The implementation of this mechanism using a branch target instruction memory is described. An analytical model of the performance of this implementation makes it possible to measure the efficiency of the mechanism with a very low computational cost. The model is used to determine the size of cache lines that maximizes the processor performance, to compare the performance of the mechanism with that of other schemes, and to analyze the performance of the mechanism with two alternative cache organizations.Peer ReviewedPostprint (published version

Using compression to identify acronyms in text

Text mining is about looking for patterns in natural language text, and may be defined as the process of analyzing text to extract information from it for particular purposes. In previous work, we claimed that compression is a key technology for text mining, and backed this up with a study that showed how particular kinds of lexical tokens---names, dates, locations, etc.---can be identified and located in running text, using compression models to provide the leverage necessary to distinguish different token types (Witten et al., 1999)Comment: 10 pages. A short form published in DCC200

Communications for Next Generation single chip computers

It is the thesis of this report that much of what is presently thought to require specialized VLSI functions might instead be achieved by combinations of fast general purpose single chip computers with upgraded communication facilities. To this end, the characteristics of applications of this nature are first surveyed briefly and some working principles established. In the light of these, three different chip philosophies are explored in some detail. This study shows that some upgrading of typical single chip I/O will definitely be necessary, but that this upgrading does not have to be complex and that true multiprocessor-multibus operation could be achieved without excessive cost

Cerebellar models of associative memory: Three papers from IEEE COMPCON spring 1989

Three papers are presented on the following topics: (1) a cerebellar-model associative memory as a generalized random-access memory; (2) theories of the cerebellum - two early models of associative memory; and (3) intelligent network management and functional cerebellum synthesis

A bibliography on parallel and vector numerical algorithms

This is a bibliography of numerical methods. It also includes a number of other references on machine architecture, programming language, and other topics of interest to scientific computing. Certain conference proceedings and anthologies which have been published in book form are listed also

A study of reverse osmosis reject water at Bukit Gambir, Tangkak Haemodialysis Centre

Water is categorized by their few aspects according to the specific feature and it function usage in a certain compatible condition. Yet with rapidly population growth increasing around the world by about 85 million per year, the accessibility for fresh water supply per persons keep declining [1]. The increasing clean water demand causes the increasing environmental risks, costs and economic exploitation as it may disturb surrounding nature which leads into the more distant sources or greater depth. At this state, the minimization of waste water produce should be focused on to prevent it become worsen

Layout level design for testability strategy applied to a CMOS cell library

The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cell

Coin Tossing is Strictly Weaker Than Bit Commitment

We define cryptographic assumptions applicable to two mistrustful parties who each control two or more separate secure sites between which special relativity guarantees a time lapse in communication. We show that, under these assumptions, unconditionally secure coin tossing can be carried out by exchanges of classical information. We show also, following Mayers, Lo and Chau, that unconditionally secure bit commitment cannot be carried out by finitely many exchanges of classical or quantum information. Finally we show that, under standard cryptographic assumptions, coin tossing is strictly weaker than bit commitment. That is, no secure classical or quantum bit commitment protocol can be built from a finite number of invocations of a secure coin tossing black box together with finitely many additional information exchanges.Comment: Final version; to appear in Phys. Rev. Let

A new distributed real-time controller for robotics applications

A description is given of a dual-board real-time distributed control module based on the INMOS T414/T800 transputers. The CPU board provides fast external memory, support for the four 10-MHz serial transputer links including two fiber-optic links, and an I/O expansion connector. The board\u27s backplane connector is pin-compatible with the INMOS ITEM development system. The plug-in I/O board provides a bidirectional latched 32-bit I/O bus with full handshaking support. Half of this board is allotted to a wire-wrap prototyping area allowing for customization to specific I/O needs. It is asserted that an easily configurable network built from this low-cost modular design should be able to tackle the most demanding real-time control applications, with respect to computation as well as I/O requirements. A description is given of two particular applications presently underway in the Yale Robotics Laboratory