Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge. On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques. This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator

A 0.3 V rail-to-rail ultra-low-power OTA with improved bandwidth and slew rate

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier

A HIGH PERFORMANCE FULLY DIFFERENTIAL PURE CURRENT MODE OPERATIONAL AMPLIFIER AND ITS APPLICATIONS

In this paper a novel high performance all current-mode fully-differential (FD) Current mode Operational Amplifier (COA) in BIPOLAR technology is presented. The unique true current mode simple structure grants the proposed COA the largest yet reported unity gain frequency while providing low voltage low power operation. Benefiting from some novel ideas, it also exhibits high gain, high common mode rejection ratio (CMRR), high power supply rejection ratio (PSRR), high output impedance, low input impedance and most importantly high current drive capability. Its most important parameters are derived and its performance is proved by PSPICE simulations using 0.8 μm BICMOS process parameters at supply voltage of ±1.2V indicating the values of 82.4 dB,52.3º, 31.5 Ω, 31.78 MΩ, 179.2 dB, 2 mW and 698 MHz for gain, phase margin, input impedance, output impedance, CMRR, power and unity gain frequency respectively. Its CMRR also shows very high frequency of 2.64 GHz at zero dB. Its very high PSRR+/PSRR- of 182 dB/196 dB makes the proposed COA a highly suitable block in Mixed-Mode (SOC) chips. Most favourably it can deliver up to ±1.5 mA yielding a high current drive capability exceeding 25. To demonstrate the performance of the proposed COA, it is used to realize a constant bandwidth voltage amplifier and a high performance Rm amplifier

Low-Voltage Bulk-Driven Amplifier Design and Its Application in Implantable Biomedical Sensors

The powering unit usually represents a significant component of the implantable biomedical sensor system since the integrated circuits (ICs) inside for monitoring different physiological functions consume a great amount of power. One method to reduce the volume of the powering unit is to minimize the power supply voltage of the entire system. On the other hand, with the development of the deep sub-micron CMOS technologies, the minimum channel length for a single transistor has been scaled down aggressively which facilitates the reduction of the chip area as well. Unfortunately, as an inevitable part of analytic systems, analog circuits such as the potentiostat are not amenable to either low-voltage operations or short channel transistor scheme. To date, several proposed low-voltage design techniques have not been adopted by mainstream analog circuits for reasons such as insufficient transconductance, limited dynamic range, etc. Operational amplifiers (OpAmps) are the most fundamental circuit blocks among all analog circuits. They are also employed extensively inside the implantable biosensor systems. This work first aims to develop a general purpose high performance low-voltage low-power OpAmp. The proposed OpAmp adopts the bulk-driven low-voltage design technique. An innovative low-voltage bulk-driven amplifier with enhanced effective transconductance is developed in an n-well digital CMOS process operating under 1-V power supply. The proposed circuit employs auxiliary bulk-driven input differential pairs to achieve the input transconductance comparable with the traditional gate-driven amplifiers, without consuming a large amount of current. The prototype measurement results show significant improvements in the open loop gain (AO) and the unity-gain bandwidth (UGBW) compared to other works. A 1-V potentiostat circuit for an implantable electrochemical sensor is then proposed by employing this bulk-driven amplifier. To the best of the author’s knowledge, this circuit represents the first reported low-voltage potentiostat system. This 1-V potentiostat possesses high linearity which is comparable or even better than the conventional potentiostat designs thanks to this transconductance enhanced bulk-driven amplifier. The current consumption of the overall potentiostat is maintained around 22 microampere. The area for the core layout of the integrated circuit chip is 0.13 mm2 for a 0.35 micrometer process

A 0.3 V, rail-to-rail, ultralow-power, non-tailed, body-driven, sub-threshold amplifier

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations

Design of Low Power CMOS Bioamplifier in 250 nm and 90 nm Technology Node

The advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has enabled a better design in bioamplifier for electroencephalography (EEG) and electrocardiogram (ECG) signals acquisition systems. Bioamplifier can be designed using two-stage CMOS operational transconductance amplifier (OTA). This paper presents the performance of CMOS bioamplifier which had been designed using two CMOS technology; one using 250 nm and the other in 90 nm technology. The 250 nm CMOS bioamplifier operates with ±2.5 V voltage supply and has open loop gain of 82 dB and the common mode rejection ratio (CMRR) of 92 dB, meanwhile the 90 nm CMOS bioamplifier operates with ±1.2 V voltage supply and has open loop gain of 72.9 dB and common mode rejection ratio (CMRR) of 73.03 dB. The power consumed by the OTA bioamplifier is 5.56 mW for the 250 nm amplifier and 15.53 µW for the 90 nm amplifier

Low-Voltage Analog Circuit Design Using the Adaptively Biased Body-Driven Circuit Technique

The scaling of MOSFET dimensions and power supply voltage, in conjunction with an increase in system- and circuit-level performance requirements, are the most important factors driving the development of new technologies and design techniques for analog and mixed-signal integrated circuits. Though scaling has been a fact of life for analog circuit designers for many years, the approaching 1-V and sub-1-V power supplies, combined with applications that have increasingly divergent technology requirements, means that the analog and mixed-signal IC designs of the future will probably look quite different from those of the past. Foremost among the challenges that analog designers will face in highly scaled technologies are low power supply voltages, which limit dynamic range and even circuit functionality, and ultra-thin gate oxides, which give rise to significant levels of gate leakage current. The goal of this research is to develop novel analog design techniques which are commensurate with the challenges that designers will face in highly scaled CMOS technologies. To that end, a new and unique body-driven design technique called adaptive gate biasing has been developed. Adaptive gate biasing is a method for guaranteeing that MOSFETs in a body-driven simple current mirror, cascode current mirror, or regulated cascode current source are biased in saturation—independent of operating region, temperature, or supply voltage—and is an enabling technology for high-performance, low-voltage analog circuits. To prove the usefulness of the new design technique, a body-driven operational amplifier that heavily leverages adaptive gate biasing has been developed. Fabricated on a 3.3-V/0.35-μm partially depleted silicon-onv-insulator (PD-SOI) CMOS process, which has nMOS and pMOS threshold voltages of 0.65 V and 0.85 V, respectively, the body-driven amplifier displayed an open-loop gain of 88 dB, bandwidth of 9 MHz, and PSRR greater than 50 dB at 1-V power supply

High-frequency two-input CMOS OTA for continuous-time filter applications

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”A high-frequency fully differential CMOS operational transconductance amplifier (OTA) is presented for continuous-time filter applications in the megahertz range. The proposed design technique combines a linear cross-coupled quad input stage with an enhanced folded-cascode circuit to increase the output resistance of the amplifier. SPICE simulations show that DC-gain enhancement can be obtained without significant bandwidth limitation. The two-input OTA developed is used in high-frequency tuneable filter design based on IFLF and LC ladder simulation structures. Simulated results of parameters and characteristics of the OTA and filters in a standard 1.2 μm CMOS process (MOSIS) are presented. A tuning circuit is also discussed.Peer reviewe