1,288 research outputs found
Principles of Neuromorphic Photonics
In an age overrun with information, the ability to process reams of data has
become crucial. The demand for data will continue to grow as smart gadgets
multiply and become increasingly integrated into our daily lives.
Next-generation industries in artificial intelligence services and
high-performance computing are so far supported by microelectronic platforms.
These data-intensive enterprises rely on continual improvements in hardware.
Their prospects are running up against a stark reality: conventional
one-size-fits-all solutions offered by digital electronics can no longer
satisfy this need, as Moore's law (exponential hardware scaling),
interconnection density, and the von Neumann architecture reach their limits.
With its superior speed and reconfigurability, analog photonics can provide
some relief to these problems; however, complex applications of analog
photonics have remained largely unexplored due to the absence of a robust
photonic integration industry. Recently, the landscape for
commercially-manufacturable photonic chips has been changing rapidly and now
promises to achieve economies of scale previously enjoyed solely by
microelectronics.
The scientific community has set out to build bridges between the domains of
photonic device physics and neural networks, giving rise to the field of
\emph{neuromorphic photonics}. This article reviews the recent progress in
integrated neuromorphic photonics. We provide an overview of neuromorphic
computing, discuss the associated technology (microelectronic and photonic)
platforms and compare their metric performance. We discuss photonic neural
network approaches and challenges for integrated neuromorphic photonic
processors while providing an in-depth description of photonic neurons and a
candidate interconnection architecture. We conclude with a future outlook of
neuro-inspired photonic processing.Comment: 28 pages, 19 figure
An Optoelectronic Stimulator for Retinal Prosthesis
Retinal prostheses require the presence of viable population of cells in the inner retina. Evaluations
of retina with Age-Related Macular Degeneration (AMD) and Retinitis Pigmentosa (RP)
have shown a large number of cells remain in the inner retina compared with the outer retina.
Therefore, vision loss caused by AMD and RP is potentially treatable with retinal prostheses.
Photostimulation based retinal prostheses have shown many advantages compared with retinal
implants. In contrary to electrode based stimulation, light does not require mechanical contact.
Therefore, the system can be completely external and not does have the power and degradation
problems of implanted devices. In addition, the stimulating point is
flexible and does not require
a prior decision on the stimulation location. Furthermore, a beam of light can be projected on
tissue with both temporal and spatial precision. This thesis aims at fi nding a feasible solution
to such a system.
Firstly, a prototype of an optoelectronic stimulator was proposed and implemented by using the
Xilinx Virtex-4 FPGA evaluation board. The platform was used to demonstrate the possibility
of photostimulation of the photosensitized neurons. Meanwhile, with the aim of developing
a portable retinal prosthesis, a system on chip (SoC) architecture was proposed and a wide
tuning range sinusoidal voltage-controlled oscillator (VCO) which is the pivotal component of
the system was designed. The VCO is based on a new designed Complementary Metal Oxide
Semiconductor (CMOS) Operational Transconductance Ampli er (OTA) which achieves a good
linearity over a wide tuning range. Both the OTA and the VCO were fabricated in the AMS
0.35 µm CMOS process. Finally a 9X9 CMOS image sensor with spiking pixels was designed.
Each pixel acts as an independent oscillator whose frequency is controlled by the incident light
intensity. The sensor was fabricated in the AMS 0.35 µm CMOS Opto Process. Experimental
validation and measured results are provided
Silicon-on-insulator-based complementary metal oxide semiconductor integrated optoelectronic platform for biomedical applications
Microscale optical devices enabled by wireless power harvesting and telemetry facilitate manipulation and testing of localized biological environments (e.g., neural recording and stimulation, targeted delivery to cancer cells). Design of integrated microsystems utilizing optical power harvesting and telemetry will enable complex in vivo applications like actuating a single nerve, without the difficult requirement of extreme optical focusing or use of nanoparticles. Silicon-on-insulator (SOI)-based platforms provide a very powerful architecture for such miniaturized platforms as these can be used to fabricate both optoelectronic and microelectronic devices on the same substrate. Near-infrared biomedical optics can be effectively utilized for optical power harvesting to generate optimal results compared with other methods (e.g., RF and acoustic) at submillimeter size scales intended for such designs. We present design and integration techniques of optical power harvesting structures with complementary metal oxide semiconductor platforms using SOI technologies along with monolithically integrated electronics. Such platforms can become the basis of optoelectronic biomedical systems including implants and lab-on-chip systems
Beyond solid-state lighting: Miniaturization, hybrid integration, and applications og GaN nano- and micro-LEDs
Gallium Nitride (GaN) light-emitting-diode (LED) technology has been the revolution in modern lighting. In the last decade, a huge global market of efficient, long-lasting and ubiquitous white light sources has developed around the inception of the Nobel-price-winning blue GaN LEDs. Today GaN optoelectronics is developing beyond lighting, leading to new and innovative devices, e.g. for micro-displays, being the core technology for future augmented reality and visualization, as well as point light sources for optical excitation in communications, imaging, and sensing. This explosion of applications is driven by two main directions: the ability to produce very small GaN LEDs (microLEDs and nanoLEDs) with high efficiency and across large areas, in combination with the possibility to merge optoelectronic-grade GaN microLEDs with silicon microelectronics in a fully hybrid approach. GaN LED technology today is even spreading into the realm of display technology, which has been occupied by organic LED (OLED) and liquid crystal display (LCD) for decades. In this review, the technological transition towards GaN micro- and nanodevices beyond lighting is discussed including an up-to-date overview on the state of the art
A scalable optoelectronic neural probe architecture with self-diagnostic capability
There is a growing demand for the development of new types of implantable optoelectronics to support both basic neuroscience and optogenetic treatments for neurological disorders. Target specification requirements include multi-site optical stimulation, programmable radiance profile, safe operation, and miniaturization. It is also preferable to have a simple serial interface rather than large numbers of control lines. This paper demonstrates an optrode structure comprising of a standard complementary metal-oxide-semiconductor process with 18 optical stimulation drivers. Furthermore, diagnostic sensing circuitry is incorporated to determine the long-term functionality of the photonic elements. A digital control system is incorporated to allow independent multisite control and serial communication with external control units
Spatio-temporal Learning with Arrays of Analog Nanosynapses
Emerging nanodevices such as resistive memories are being considered for
hardware realizations of a variety of artificial neural networks (ANNs),
including highly promising online variants of the learning approaches known as
reservoir computing (RC) and the extreme learning machine (ELM). We propose an
RC/ELM inspired learning system built with nanosynapses that performs both
on-chip projection and regression operations. To address time-dynamic tasks,
the hidden neurons of our system perform spatio-temporal integration and can be
further enhanced with variable sampling or multiple activation windows. We
detail the system and show its use in conjunction with a highly analog
nanosynapse device on a standard task with intrinsic timing dynamics- the TI-46
battery of spoken digits. The system achieves nearly perfect (99%) accuracy at
sufficient hidden layer size, which compares favorably with software results.
In addition, the model is extended to a larger dataset, the MNIST database of
handwritten digits. By translating the database into the time domain and using
variable integration windows, up to 95% classification accuracy is achieved. In
addition to an intrinsically low-power programming style, the proposed
architecture learns very quickly and can easily be converted into a spiking
system with negligible loss in performance- all features that confer
significant energy efficiency.Comment: 6 pages, 3 figures. Presented at 2017 IEEE/ACM Symposium on Nanoscale
architectures (NANOARCH
Progress in the Smart Pixel Technologies
The purpose of this paper is to review the recent progress in the developing smart pixel technologies. The paper begins by reviewing some of the rapidly evolving smart pixel terminologies. It then describes several of the smart pixel technologies that have recently emerged. Finally, it outlines the performance of these technologies in both device complexity and aggregate capacity. The reviewed SPA technologies include both the modulator-based FET-SEED, hybrid CMOS-SEED, and LCOS smart pixels and the source-based hybrid VCSEL/MSM, ELO, flip-chip-bonded VCSEL/MSM, and monolithic MSM/MESFET/VCSEL smart pixels
Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology
This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJT’s connected in a Darlington structure. Pixel smartness is achieved by exploiting the Cellular Neural Network paradigm [1], [2], incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-µm technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm2, with a power consumption down to 105 µW/unit and image processing times below 2 µs
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