Design and characterization of a low voltage CMOS ASIC for medical instrumentation

The acquisition of biomedical signals requires analogue to digital converters of high resolution, low voltage of power and low consumption. The solution for this need is the use of new sigma delta conversion architectures such as the one tested in this Bachelor Thesis. This work covers the design of the instrumentation necessary for the operation of Application-Specific Integrated Circuit Sigma Delta Analog-to-Digital Converter (ASIC ADC) that is already manufactured and its integration into a Printed Circuit Board (PCB). It also includes the development of the necessary software that facilitates the accomplishment of the necessary tests and the analysis of the data that will allow to characterize the operation of the fabricated prototype. Finally, the results and conclusions of the project will be described. The ASIC to be tested in this Bachelor Thesis consists of a180-nm Complementary Metal-Oxide Semiconductor (CMOS) bandpass ADC developed to fulfil the specifications of a fully-integrated receiver for Magnetic Resonance Imaging (MRI). Integrating an integrated CMOS receiver into a single chip will help improve image quality by avoiding the use of many coaxial cables that are used to connect the Radio Frequency (RF) coils to the scanning hardware. The proposal made is a very simple Low-IF receiver characteristics in which a continuous time Low-IF bandpass ADC is the most efficient architecture. The circuit in continuous time replaces the classic filter only thus, an anti-alias filter would be necessary. In addition, the bandpass filter assists in the attenuation of the quantization noise in the bandwidth of interest, while at the same time the stability of the system is easily achieved due to the selected Low-IF.Ingeniería Biomédic

Review on X-ray detectors based on scintillators and CMOS technology

This article describes the theoretical basis, design and implementation of X-ray microdetectors based on scintillating materials and CMOS technology. The working principle of such microdetectors consists in the absorption of X-rays by scintillators, which produce visible light. The visible light is then detected and converted into electric signals by means of photodetectors. In order to understand such detectors, several issues related to its implementation are presented in this article, namely: Production of X-rays and interaction between them and matter - the first step necessary to the detection of X-rays is that they must be absorbed by some material, in this case by a scintillator; Radiation detectors - there are several types of detectors, namely: pn junctions, photoconductors, based on thermal effects and scintillators; Fabrication of scintillator arrays - after the X-ray radiation is absorbed by a scintillator, this material emits visible light whose intensity is proportional to the total energy of the absorbed X-rays; Optical interfaces between scintillators and photodetectors - the visible light generated by scintillators must arrive to the photodetectors, so, it is necessary to have an interface between the scintillators and the photodetectors that ideally does not introduce losses; Photodetectors and interface electronics - the visible light is absorbed by the photodetectors and converted into electrical signals, which are finally converted into digital images by means of interface electronics. The article presents some promising patents on X-ray detectors based on scintillators and CMOS technology.Fundação para a Ciência e a Tecnologia (FCT) - Bolsa SFRH/BSAB/1014/201

Design, analysis and evaluation of sigma-delta based beamformers for medical ultrasound imaging applications

The inherent analogue nature of medical ultrasound signals in conjunction with the abundant merits provided by digital image acquisition, together with the increasing use of relatively simple front-end circuitries, have created considerable demand for single-bit beamformers in digital ultrasound imaging systems. Furthermore, the increasing need to design lightweight ultrasound systems with low power consumption and low noise, provide ample justification for development and innovation in the use of single-bit beamformers in ultrasound imaging systems. The overall aim of this research program is to investigate, establish, develop and confirm through a combination of theoretical analysis and detailed simulations, that utilize raw phantom data sets, suitable techniques for the design of simple-to-implement hardware efficient digital ultrasound beamformers to address the requirements for 3D scanners with large channel counts, as well as portable and lightweight ultrasound scanners for point-of-care applications and intravascular imaging systems. In addition, the stability boundaries of higher-order High-Pass (HP) and Band-Pass (BP) Σ−Δ modulators for single- and dual- sinusoidal inputs are determined using quasi-linear modeling together with the describing-function method, to more accurately model the modulator quantizer. The theoretical results are shown to be in good agreement with the simulation results for a variety of input amplitudes, bandwidths, and modulator orders. The proposed mathematical models of the quantizer will immensely help speed up the design of higher order HP and BP Σ−Δ modulators to be applicable for digital ultrasound beamformers. Finally, a user friendly design and performance evaluation tool for LP, BP and HP modulators is developed. This toolbox, which uses various design methodologies and covers an assortment of modulators topologies, is intended to accelerate the design process and evaluation of modulators. This design tool is further developed to enable the design, analysis and evaluation of beamformer structures including the noise analyses of the final B-scan images. Thus, this tool will allow researchers and practitioners to design and verify different reconstruction filters and analyze the results directly on the B-scan ultrasound images thereby saving considerable time and effort

Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements

The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver

Study and application of direct RF power injection methodology and mitigation of electromagnetic interference in ADCs

There are many publications available in literature regarding the DPI (Direct Power Injection) technique for electronic systems, but few works specifically addressed for mixed-signal converters, which are components existent in almost all electronic devices. IEC 62132-4(International Electrotechnical Commission, 2006) and 62132-1(International Electrotechnical Commission, 2006) standards describe a method for measuring immunity of integrated circuits (IC) in the presence of conducted RF disturbances. This method ensures a high degree of repeatability and correlation of immunity measurements. Knowledge of the electromagnetic immunity of an IC allows the designer to decide if the system will need external protection, and how much effort should be directed to this solution. In this context, the purpose of this work is the study and application of the DPI methodology for injection of EMI in a mixed-signal programmable device, evaluating mitigation possibilities, with special focus on the analog-to-digital converters (ADCs). The main objective is to evaluate the impact of electromagnetic interference (EMI) on different converters (two Successive Approximation Register ADCs, operating with distinct sampling rate and a Sigma-Delta ADC) of the Cypress Semiconductor Programmable SoC (System-on-Chip), PSoC 5LP. Additionally a previously proposed fault tolerance methodology, based on triplication with hardware and time diversity is tested. Results show distinct behaviors of each converter to conducted EMI. Finally, the tested tolerance technique showed to be suitable to reduce error rate of such data acquisition system operating under EMI disturbance.Existem muitas publicações disponíveis na literatura sobre a técnica de DPI (Direct Power Injection ou injeção direta de energia) para sistemas eletrônicos, mas poucos trabalhos direcionados para conversores de sinais mistos, que são componentes existentes em quase todos os dispositivos eletrônicos. As normas IEC 62132-4 (IEC, 2006) e 62132-1 (IEC, 2006) descrevem um método para medir a imunidade de circuitos integrados (CI) na presença de distúrbios de RF conduzidos. Este método garante um alto grau de repetibilidade e correlação das medições da imunidade. O conhecimento da imunidade eletromagnética de um CI permite que o projetista decida se o sistema precisará de proteção externa e quanto esforço deve ser direcionado para esta solução. Nesse contexto, o objetivo deste trabalho é o estudo e aplicação da metodologia DPI para injeção de interferência eletromagnética em um dispositivo programável de sinal misto, avaliando as possibilidades de mitigação, com foco especial em conversores analógico-digitais (ADCs). O principal objetivo é avaliar o impacto da interferência eletromagnética em diferentes conversores (dois ADCs baseados em aproximação sucessiva, operando com taxa de amostragem distintas e um ADC do tipo Sigma-Delta) do SoC(System-on-Chip) programável da Cypress Semiconductor, PSoC 5LP. Além disso, é testada uma metodologia de tolerância a falhas proposta anteriormente, baseada em triplicação com diversidade de hardware e temporal. Os resultados mostram comportamentos distintos de cada conversor para a interferência eletromagnética conduzida. Finalmente, a técnica de tolerância testada mostrou-se adequada para reduzir a taxa de erros desse sistema de aquisição de dados operando sob perturbação eletromagnética

Linearization of Time-encoded ADCs Architectures for Smart MEMS Sensors in Low Power CMOS Technology

Mención Internacional en el título de doctorIn the last few years, the development of mobile technologies and machine learning applications has increased the demand of MEMS-based digital microphones. Mobile devices have several microphones enabling noise canceling, acoustic beamforming and speech recognition. With the development of machine learning applications the interest to integrate sensors with neural networks has increased. This has driven the interest to develop digital microphones in nanometer CMOS nodes where the microphone analog-front end and digital processing, potentially including neural networks, is integrated on the same chip. Traditionally, analog-to-digital converters (ADCs) in digital microphones have been implemented using high order Sigma-Delta modulators. The most common technique to implement these high order Sigma-Selta modulators is switchedcapacitor CMOS circuits. Recently, to reduce power consumption and make them more suitable for tasks that require always-on operation, such as keyword recognition, switched-capacitor circuits have been improved using inverter-based operational amplifier integrators. Alternatively, switched-capacitor based Sigma- Delta modulators have been replaced by continuous time Sigma-Delta converters. Nevertheless, in both implementations the input signal is voltage encoded across the modulator, making the integration in smaller CMOS nodes more challenging due to the reduced voltage supply. An alternative technique consists on encoding the input signal on time (or frequency) instead of voltage. This is what time-encoded converters do. Lately, time-encoding converters have gained popularity as they are more suitable to nanometer CMOS nodes than Sigma-Delta converters. Among the ones that have drawn more interest we find voltage-controlled oscillator based ADCs (VCOADCs). VCO-ADCs can be implemented using CMOS inverter based ring oscillators (RO) and digital circuitry. They also show noise-shaping properties. This makes them a very interesting alternative for implementation of ADCs in nanometer CMOS nodes. Nevertheless, two main circuit impairments are present in VCO-ADCs, and both come from the oscillator non-idealities. The first of them is the oscillator phase noise, that reduces the resolution of the ADC. The second is the non-linear tuning curve of the oscillator, that results in harmonic distortion at medium to high input amplitudes. In this thesis we analyze the use of time encoding ADCs for MEMS microphones with special focus on ring oscillator based ADCs (RO-ADCs). Firstly, we study the use of a dual-slope based SAR noise shaped quantizer (SAR-NSQ) in sigma-delta loops. This quantizer adds and extra level of noise-shaping to the modulator, improving the resolution. The quantizer is explained, and equations for the noise transfer function (NTF) of a third order sigma-delta using a second order filter and the NSQ are presented. Secondly, we move our attention to the topic of RO-ADCs. We present a high dynamic range MEMS microphone 130nm CMOS chip based on an open-loop VCO-ADC. This dissertation shows the implementation of the analog front-end that includes the oscillator and the MEMS interface, with a focus on achieving low power consumption with low noise and a high dynamic range. The digital circuitry is left to be explained by the coauthor of the chip in his dissertation. The chip achieves a 80dBA peak SNDR and 108dB dynamic range with a THD of 1.5% at 128 dBSPL with a power consumption of 438μW. After that, we analyze the use of a frequency-dependent-resistor (FDR) to implement an unsampled feedback loop around the oscillator. The objective is to reduce distortion. Additionally phase noise mitigation is achieved. A first topology including an operational amplifier to increase the loop gain is analyzed. The design is silicon proven in a 130 nm CMOS chip that achieves a 84 dBA peak SNDR with an analog power consumption of 600μW. A second topology without the operational amplifier is also analyzed. Two chips are designed with this topology. The first chip in 130 nm CMOS is a full VCO-ADC including the frequencyto- digital converter (F2D). This chip achieves a peak SNDR of 76.6 dBA with a power consumption of 482μW. The second chip includes only the oscillator and is implemented in 55nm CMOS. The peak SNDR is 78.15 dBA and the analog power consumption is 153μW. To finish this thesis, two circuits that use an FDR with a ring oscillator are presented. The first is a capacity-to-digital converter (CDC). The second is a filter made with an FDR and an oscillator intended for voice activity detection tasks (VAD).En los últimos años, el desarrollo de las tecnologías móviles y las aplicaciones de machine-learning han aumentado la demanda de micrófonos digitales basados en MEMS. Los dipositivos móviles tienen varios micrófonos que permiten la cancelación de ruido, el beamforming o conformación de haces y el reconocimiento de voz. Con el desarrollo de aplicaciones de aprendizaje automático, el interés por integrar sensores con redes neuronales ha aumentado. Esto ha impulsado el interés por desarrollar micrófonos digitales en nodos CMOS nanométricos donde el front-end analógico y el procesamiento digital del micrófono, que puede incluir redes neuronales, está integrado en el mismo chip. Tradicionalmente, los convertidores analógicos-digitales (ADC) en micrófonos digitales han sido implementados utilizando moduladores Sigma-Delta de orden elevado. La técnica más común para implementar estos moduladores Sigma- Delta es el uso de circuitos CMOS de capacidades conmutadas. Recientemente, para reducir el consumo de potencia y hacerlos más adecuados para las tareas que requieren una operación continua, como el reconocimiento de palabras clave, los convertidores Sigma-Delta de capacidades conmutadas has sido mejorados con el uso de integradores implementados con amplificadores operacionales basados en inversores CMOS. Alternativamente, los Sigma-Delta de capacidades conmutadas han sido reemplazados por moduladores en tiempo continuo. No obstante, en ambas implementaciones, la señal de entrada es codificada en voltaje durante el proceso de conversión, lo que hace que la integración en nodos CMOS más pequeños sea complicada debido a la menor tensión de alimentación. Una técnica alternativa consiste en codificar la señal de entrada en tiempo (o frecuencia) en lugar de tensión. Esto es lo que hacen los convertidores de codificación temporal. Recientemente, los convertidores de codificación temporal han ganado popularidad ya que son más adecuados para nodos CMOS nanométricos que los convertidores Sigma-Delta. Entre los que más interés han despertado encontramos los ADCs basados en osciladores controlados por tensión (VCO-ADC). Los VCO-ADC se pueden implementar usando osciladores en anillo (RO) implementados con inversores CMOS y circuitos digitales. Esta familia de convertidores también tiene conformado de ruido. Esto los convierte en una alternativa muy interesante para la implementación de convertidores en nodos CMOS nanométricos. Sin embargo, dos problemas principales están presentes en este tipo de ADCs debidos ambos a las no idealidades del oscilador. El primero de los problemas es la presencia de ruido de fase en el oscilador, lo que reduce la resolución del ADC. El segundo es la curva de conversion voltaje-frecuencia no lineal del oscilador, lo que causa distorsión a amplitudes medias y altas. En esta tesis analizamos el uso de ADCs de codificación temporal para micrófonos MEMS, con especial interés en ADCS basados en osciladores de anillo (RO-ADC). En primer lugar, estudiamos el uso de un cuantificador SAR con conformado de ruido (SAR-NSQ) en moduladores Sigma-Delta. Este cuantificador agrega un orden adicional de conformado de ruido al modulador, mejorando la resolución. En este documento se explica el cuantificador y obtienen las ecuaciones para la función de transferencia de ruido (NTF) de un sigma-delta de tercer orden usando un filtro de segundo orden y el NSQ. En segundo lugar, dirigimos nuestra atención al tema de los RO-ADC. Presentamos el chip de un micrófono MEMS de alto rango dinámico en CMOS de 130 nm basado en un VCO-ADC de bucle abierto. En esta tesis se explica la implementación del front-end analógico que incluye el oscilador y la interfaz con el MEMS. Esta implementación se ha llevado a cabo con el objetivo de lograr un bajo consumo de potencia, un bajo nivel de ruido y un alto rango dinámico. La descripción del back-end digital se deja para la tesis del couator del chip. La SNDR de pico del chip es de 80dBA y el rango dinámico de 108dB con una THD de 1,5% a 128 dBSPL y un consumo de potencia de 438μW. Finalmente, se analiza el uso de una resistencia dependiente de frecuencia (FDR) para implementar un bucle de realimentación no muestreado alrededor del oscilador. El objetivo es reducir la distorsión. Además, también se logra la mitigación del ruido de fase del oscilador. Se analyza una primera topologia de realimentación incluyendo un amplificador operacional para incrementar la ganancia de bucle. Este diseño se prueba en silicio en un chip CMOS de 130nm que logra un pico de SNDR de 84 dBA con un consumo de potencia de 600μW en la parte analógica. Seguidamente, se analiza una segunda topología sin el amplificador operacional. Se fabrican y miden dos chips diseñados con esta topologia. El primero de ellos en CMOS de 130 nm es un VCO-ADC completo que incluye el convertidor de frecuencia a digital (F2D). Este chip alcanza un pico SNDR de 76,6 dBA con un consumo de potencia de 482μW. El segundo incluye solo el oscilador y está implementado en CMOS de 55nm. El pico SNDR es 78.15 dBA y el el consumo de potencia analógica es de 153μW. Para cerrar esta tesis, se presentan dos circuitos que usan la FDR con un oscilador en anillo. El primero es un convertidor de capacidad a digital (CDC). El segundo es un filtro realizado con una FDR y un oscilador, enfocado a tareas de detección de voz (VAD).Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Antonio Jesús Torralba Silgado.- Secretaria: María Luisa López Vallejo.- Vocal: Pieter Rombout