Mixed-signal CNN array chips for image processing

Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates for the implementation of image processing algorithms using VLSI analog parallel arrays. However, the design of general purpose, programmable CNN chips with dimensions required for practical applications raises many challenging problems to analog designers. This is basically due to the fact that large silicon area means large development cost, large spatial deviations of design parameters and low production yield. CNN designers must face different issues to keep reasonable enough accuracy level and production yield together with reasonably low development cost in their design of large CNN chips. This paper outlines some of these major issues and their solutions

Fast, non-monte-carlo estimation of transient performance variation due to device mismatch

This paper describes an efficient way of simulating the effects of device random mismatch on circuit transient characteristics, such as variations in delay or in frequency. The proposed method models DC random offsets as equivalent AC pseudo-noises and leverages the fast, linear periodically time-varying (LPTV) noise analysis available from RF circuit simulators. Therefore, the method can be considered as an extension to DC match analysis and offers a large speed-up compared to the traditional Monte-Carlo analysis. Although the assumed linear perturbation model is valid only for small variations, it enables easy ways to estimate correlations among variations and identify the most sensitive design parameters to mismatch, all at no additional simulation cost. Three benchmarks measuring the variations in the input offset voltage of a clocked comparator, the delay of a logic path, and the frequency of an oscillator demonstrate the speed improvement of about 100-1000x compared to a 1000-point Monte-Carlo method

Design, fabrication, characterization and reliability study of CMOS-MEMS Lorentz-Force magnetometers

Tesi en modalitat de compendi de publicacionsToday, the most common form of mass-production semiconductor device fabrication is Complementary Metal-Oxide Semiconductor (CMOS) technology. The dedicated Integrated Circuit (IC) interfaces of commercial sensors are manufactured using this technology. The sensing elements are generally implemented using Micro-Electro-Mechanical-Systems (MEMS), which need to be manufactured using specialized micro-machining processes. Finally, the CMOS circuitry and the MEMS should ideally be combined in a single package. For some applications, integration of CMOS electronics and MEMS devices on a single chip (CMOS-MEMS) has the potential of reducing fabrication costs, size, parasitics and power consumption, compared to other integration approaches. Remarkably, a CMOS-MEMS device may be built with the back-end-of-line (BEOL) layers of the CMOS process. But, despite its advantages, this particular approach has proven to be very challenging given the current lack of commercial products in the market. The main objective of this Thesis is to prove that a high-performance MEMS, sealed and packaged in a standard package, may be accurately modeled and manufactured using the BEOL layers of a CMOS process in a reliable way. To attain this, the first highly reliable novel CMOS-MEMS Lorentz Force Magnetometer (LFM) was successfully designed, modeled, manufactured, characterized and subjected to several reliability tests, obtaining a comparable or superior performance to the typical solid-state magnetometers used in current smartphones. A novel technique to avoid magnetic offsets, the main drawback of LFMs, was presented and its performance confirmed experimentally. Initially, the issues encountered in the manufacturing process of MEMS using the BEOL layers of the CMOS process were discouraging. Vapor HF release of MEMS structures using the BEOL of CMOS wafers resulted in undesirable damaging effects that may lead to the conclusion that this manufacturing approach is not feasible. However, design techniques and workarounds for dealing with the observed issues were devised, tested and implemented in the design of the LFM presented in this Thesis, showing a clear path to successfully fabricate different MEMS devices using the BEOL.Hoy en día, la forma más común de producción en masa es una tecnología llamada Complementary Metal-Oxide Semiconductor (CMOS). La interfaz de los circuitos integrados (IC) de sensores comerciales se fabrica usando, precisamente, esta tecnología. Actualmente es común que los sensores se implementen usando Sistemas Micro-Electro-Mecánicos (MEMS), que necesitan ser fabricados usando procesos especiales de micro-mecanizado. En un último paso, la circuitería CMOS y el MEMS se combinan en un único elemento, llamado package. En algunas aplicaciones, la integración de la electrónica CMOS y los dispositivos MEMS en un único chip (CMOS-MEMS) alberga el potencial de reducir los costes de fabricación, el tamaño, los parásitos y el consumo, al compararla con otras formas de integración. Resulta notable que un dispositivo CMOS-MEMS pueda ser construido con las capas del back-end-of-line (BEOL) de un proceso CMOS. Pero, a pesar de sus ventajas, este enfoque ha demostrado ser un gran desafío como demuestra la falta de productos comerciales en el mercado. El objetivo principal de esta Tesis es probar que un MEMS de altas prestaciones, sellado y empaquetado en un encapsulado estándar, puede ser correctamente modelado y fabricado de una manera fiable usando las capas del BEOL de un proceso CMOS. Para probar esto mismo, el primer magnetómetro CMOS-MEMS de fuerza de Lorentz (LFM) fue exitosamente diseñado, modelado, fabricado, caracterizado y sometido a varias pruebas de fiabilidad, obteniendo un rendimiento comparable o superior al de los típicos magnetómetros de estado sólido, los cuales son usados en móviles actuales. Cabe destacar que en esta Tesis se presenta una novedosa técnica con la que se evitan offsets magnéticos, el mayor inconveniente de los magnetómetros de fuerza Lorentz. Su efectividad fue confirmada experimentalmente. En los inicios, los problemas asociados al proceso de fabricación de MEMS usando las capas BEOL de obleas CMOS resultaba desalentador. Liberar estructuras MEMS hechas con obleas CMOS con vapor de HF producía efectos no deseados que bien podrían llevar a la conclusión de que este enfoque de fabricación no es viable. Sin embargo, se idearon y probaron técnicas de diseño especiales y soluciones ad-hoc para contrarrestar estos efectos no deseados. Se implementaron en el diseño del magnetómetro de Lorentz presentado en esta Tesis, arrojando excelentes resultados, lo cual despeja el camino hacia la fabricación de diferentes dispositivos MEMS usando las capas BEOL.Postprint (published version

High-speed communication circuits: voltage control oscillators and VCO-derived filters

Voltage Controlled Oscillators (VCO) and filters are the two main topics of focus in this dissertation.;A temperature and process compensated VCO, which is designed to operate at 2 GHz, and whose frequency variation due to incoming data is limited to 1% of its center frequency was presented. The test results show that, without process changes present, the frequency variation due to a temperature change over 0°C to 100°C is around 1.1% of its center frequency. This is a reduction of a factor of 10 when compared to the temperature variation of a conventional VCO.;A new method of designing continuous-time monolithic filters derived from well-known voltage controlled oscillators (VCOs) was introduced. These VCO-derived filters are capable of operating at very high frequencies in standard CMOS processes. Prototype low-pass and band-pass filters designed in a TSMC 0.25 mum process are discussed. Simulation results for the low-pass filter designed for a cutoff frequency of 4.3 GHz show a THD of -40 dB for a 200 mV peak-peak sinusoidal input. The band-pass filter has a resonant frequency programmable from 2.3 GHz to 3.1 GHz, a programmable Q from 3 to 85, and mid-band THD of -40 dB for an 80 mV peak-peak sinusoidal input signal.;A third contribution in this dissertation was the design of a new current mirror with accurate mirror gain for low beta bipolar transistors. High mirror gain accuracy is achieved by using a split-collector transistor to compensate for base currents of the source-coupled

High performance readout circuits and devices for Lorentz force resonant CMOS-MEMS magnetic sensors

In the last decades, sensing capabilities of martphones have greatly improved since the early mobile phones of the 90’s. Moreover, wearables and the automotive industry require increasing electronics and sensing sophistication. In such echnological advance, Micro Electro Mechanical Systems (MEMS) have played an important role as accelerometers and gyroscopes were the first sensors based on MEMS technology massively introduced in the market. In contrast, it still does not exist a commercial MEMS-based compass, even though Lorentz force MEMS magnetometers were first proposed in the late 90’s. Currently, Lorentz force MEMS magnetometers have been under the spotlight as they can offer an integrated solution to nowadays sensing power. As a consequence, great advances have been achieved, but various bottlenecks limit the introduction of Lorentz force MEMS compasses in the market. First, current MEMS magnetometers require high current consumption and high biasing voltages to achieve good sensitivities. Moreover, even though devices with excellent performance and sophistication are found in the literature, there is still a lack of research on the readout electronic circuits, specially in the digital signal processing, and closed loop control. Second, most research outcomes rely on custom MEMS fabrication rocesses to manufacture the devices. This is the same approach followed in current commercial MEMS, but it requires different fabrication processes for the electronics and the MEMS. As a consequence, manufacturing cost is high and sensor performance is affected by the MEMS-electronics interface parasitics. This dissertation presents potential solutions to these issues in order to pave the road to the commercialization of Lorentz force MEMS compasses. First, a complete closed loop, digitally controlled readout system is proposed. The readout circuitry, implemented with off-the-shelf commercial components, and the digital control, on an FPGA, are proposed as a proof of concept of the feasibility, and potential benefits, of such architecture. The proposed system has a measured noise of 550 nT / vHz while the MEMS is biased with 300 µA rms and V = 1 V . Second, various CMOS-MEMS magnetometers have been designed using the BEOL part of the TSMC and SMIC 180 nm standard CMOS processes, and wet and vapor etched. The devices measurement and characterisation is used to analyse the benefits and drawbacks of each design as well as releasing process. Doing so, a high volume manufacturing viability can be performed. Yield values as high as 86% have been obtained for one device manufactured in a SMIC 180 nm full wafer run, having a sensitivity of 2.82 fA/µT · mA and quality factor Q = 7.29 at ambient pressure. While a device manufactured in TSMC 180 nm has Q = 634.5 and a sensitivity of 20.26 fA/µT ·mA at 1 mbar and V = 1 V. Finally, an integrated circuit has been designed that contains all the critical blocks to perform the MEMS signal readout. The MEMS and the electronics have been manufactured using the same die area and standard TSMC 180 nm process in order to reduce parasitics and improve noise and current consumption. Simulations show that a resolution of 8.23 µT /mA for V = 1 V and BW = 10 Hz can be achieved with the designed device.En les últimes dècades, tenint en compte els primers telèfons mòbils dels anys 90, les capacitats de sensat dels telèfons intel·ligents han millorat notablement. A més, la indústria automobilística i de wearables necessiten cada cop més sofisticació en el sensat. Els Micro Electro Mechanical Systems (MEMS) han tingut un paper molt important en aquest avenç tecnològic, ja que acceleròmetres i giroscopis varen ser els primers sensors basats en la tecnologia MEMS en ser introduïts massivament al mercat. En canvi, encara no existeix en la indústria una brúixola electrònica basada en la tecnologia MEMS, tot i que els magnetòmetres MEMS varen ser proposats per primera vegada a finals dels anys 90. Actualment, els magnetòmetres MEMS basats en la força de Lorentz són el centre d'atenció donat que poden oferir una solució integrada a les capacitats de sensat actuals. Com a conseqüència, s'han aconseguit grans avenços encara que existeixen diversos colls d'ampolla que encara limiten la introducció al mercat de brúixoles electròniques MEMS basades en la força de Lorentz. Per una banda, els agnetòmetres MEMS actuals necessiten un consum de corrent i un voltatge de polarització elevats per aconseguir una bona sensibilitat. A més, tot i que a la literatura hi podem trobar dispositius amb rendiments i sofisticació excel·lents, encara existeix una manca de recerca en el circuit de condicionament, especialment de processat digital i control del llaç. Per altra banda, moltes publicacions depenen de processos de fabricació de MEMS fets a mida per fabricar els dispositius. Aquesta és la mateixa aproximació que s'utilitza actualment en la indústria dels MEMS, però té l'inconvenient que requereix processos de fabricació diferents pels MEMS i l’electrònica. Per tant, el cost de fabricació és alt i el rendiment del sensor queda afectat pels paràsits en la interfície entre els MEMS i l'electrònica. Aquesta tesi presenta solucions potencials a aquests problemes amb l'objectiu d'aplanar el camí a la comercialització de brúixoles electròniques MEMS basades en la força de Lorentz. En primer lloc, es proposa un circuit de condicionament complet en llaç tancat controlat digitalment. Aquest s'ha implementat amb components comercials, mentre que el control digital del llaç s'ha implementat en una FPGA, tot com una prova de concepte de la viabilitat i beneficis potencials que representa l'arquitectura proposada. El sistema presenta un soroll de 550 nT / vHz quan el MEMS està polaritzat amb 300 µArms i V = 1 V . En segon lloc, s'han dissenyat varis magnetòmetres CMOS-MEMS utilitzant la part BEOL dels processos CMOS estàndard de TSMC i SMIC 180 nm, que després s'han alliberat amb líquid i gas. La mesura i caracterització dels dispositius s’ha utilitzat per analitzar els beneficis i inconvenients de cada disseny i procés d’alliberament. D'aquesta manera, s'ha pogut realitzar un anàlisi de la viabilitat de la seva fabricació en massa. S'han obtingut valors de yield de fins al 86% per un dispositiu fabricat amb SMIC 180 nm en una oblia completa, amb una sensibilitat de 2.82 fA/µT · mA i un factor de qualitat Q = 7.29 a pressió ambient. Per altra banda, el dispositiu fabricat amb TSMC 180 nm presenta una Q = 634.5 i una sensibilitat de 20.26 fA/µT · mA a 1 mbar amb V = 1 V. Finalment, s'ha dissenyat un circuit integrat que conté tots els blocs per a realitzar el condicionament de senyal del MEMS. El MEMS i l'electrònica s'han fabricat en el mateix dau amb el procés estàndard de TSMC 180 nm per tal de reduir paràsits i millorar el soroll i el consum de corrent. Les simulacions mostren una resolució de 8.23 µT /mA amb V = 1 V i BW = 10 Hz pel dispositiu dissenyat

Characterization of process variability and robust optimization of analog circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.Includes bibliographical references (p. 161-174).Continuous scaling of CMOS technology has enabled dramatic performance enhancement of CMOS devices and has provided speed, power, and density improvement in both digital and analog circuits. CMOS millimeter-wave applications operating at more than 50GHz frequencies has become viable in sub-100nm CMOS technologies, providing advantages in cost and high density integration compared to other heterogeneous technologies such as SiGe and III-V compound semiconductors. However, as the operating frequency of CMOS circuits increases, it becomes more difficult to obtain sufficiently wide operating ranges for robust operation in essential analog building blocks such as voltage-controlled oscillators (VCOs) and frequency dividers. The fluctuations of circuit parameters caused by the random and systematic variations in key manufacturing steps become more significant in nano-scale technologies. The process variation of circuit performance is quickly becoming one of the main concerns in high performance analog design. In this thesis, we show design and analysis of a VCO and frequency divider operating beyond 70GHz in a 65nm SOI CMOS technology. The VCO and frequency divider employ design techniques enlarging frequency operating ranges to improve the robustness of circuit operation. Circuit performance is measured from a number of die samples to identify the statistical properties of performance variation. A back-propagation of variation (BPV) scheme based on sensitivity analysis of circuit performance is proposed to extract critical circuit parameter variation using statistical measurement results of the frequency divider. We analyze functional failure caused by performance variability, and propose dynamic and static optimization methods to improve parametric yield. An external bias control is utilized to dynamically tune the divider operating range and to compensate for performance variation. A novel time delay model of a differential CML buffer is proposed to functionally approximate the maximum operating frequency of the frequency divider, which dramatically reduces computational cost of parametric yield estimation. The functional approximation enables the optimization of the VCO and frequency divider parametric yield with a reasonable amount of simulation time.by Daihyun Lim.Ph.D

On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis

Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints. It is a well-known fact in the semiconductor industry that such goal can only be attained by means of adequate CAD methodologies, techniques, and accompanying tools. This is particularly important in analog physical synthesis (a.k.a. layout generation), where large sensitivities of the circuit performances to the many subtle details of layout implementation (device matching, loading and coupling effects, reliability, and area features are of utmost importance to analog designers), render complete automation a truly challenging task. To approach the problem, two directions have been traditionally considered, knowledge-based and optimization-based, both with their own pros and cons. Besides, recently reported solutions oriented to speed up the overall design flow by means of reuse-based practices or by cutting off time-consuming, error-prone spins between electrical and layout synthesis (a technique known as layout-aware synthesis), rely on a outstandingly rapid yet efficient layout generation method. This paper analyses the suitability of procedural layout generation based on templates (a knowledge-based approach) by examining the requirements that both layout reuse and layout-aware solutions impose, and how layout templates face them. The ability to capture the know-how of experienced layout designers and the turnaround times for layout instancing are considered main comparative aspects in relation to other layout generation approaches. A discussion on the benefit-cost trade-off of using layout templates is also included. In addition to this analysis, the paper delves deeper into systematic techniques to develop fully reusable layout templates for analog circuits, either for a change of the circuit sizing (i.e., layout retargeting) or a change of the fabrication process (i.e., layout migration). Several examples implemented with the Cadence's Virtuoso tool suite are provided as demonstration of the paper's contributions.Ministerio de Educación y Ciencia TEC2004-0175