Compressive Sensing for Spread Spectrum Receivers

With the advent of ubiquitous computing there are two design parameters of wireless communication devices that become very important power: efficiency and production cost. Compressive sensing enables the receiver in such devices to sample below the Shannon-Nyquist sampling rate, which may lead to a decrease in the two design parameters. This paper investigates the use of Compressive Sensing (CS) in a general Code Division Multiple Access (CDMA) receiver. We show that when using spread spectrum codes in the signal domain, the CS measurement matrix may be simplified. This measurement scheme, named Compressive Spread Spectrum (CSS), allows for a simple, effective receiver design. Furthermore, we numerically evaluate the proposed receiver in terms of bit error rate under different signal to noise ratio conditions and compare it with other receiver structures. These numerical experiments show that though the bit error rate performance is degraded by the subsampling in the CS-enabled receivers, this may be remedied by including quantization in the receiver model. We also study the computational complexity of the proposed receiver design under different sparsity and measurement ratios. Our work shows that it is possible to subsample a CDMA signal using CSS and that in one example the CSS receiver outperforms the classical receiver.Comment: 11 pages, 11 figures, 1 table, accepted for publication in IEEE Transactions on Wireless Communication

Adaptive code division multiple access protocol for wireless network-on-chip architectures

Massive levels of integration following Moore\u27s Law ushered in a paradigm shift in the way on-chip interconnections were designed. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn\u27t need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. However, as the bandwidth of the wireless channels is limited, an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. This thesis proposes using a multiple access mechanism such as Code Division Multiple Access (CDMA) to enable multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. It will be shown that such a hybrid wireless NoC with an efficient CDMA based MAC protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. In this work it is shown that the wireless NoC with the proposed CDMA based MAC protocol outperformed the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. Significant gains were observed in packet energy dissipation and bandwidth even with scaling the system to higher number of cores. Non-uniform traffic simulations showed that the proposed CDMA-WiNoC was consistent in bandwidth across all traffic patterns. It is also shown that the CDMA based MAC scheme does not introduce additional reliability concerns in data transfer over the on-chip wireless interconnects

WCDMA in Malaysia

Wideband Code Division Multiple Access (WCDMA) A 3G highspeed digital data service provided by cellular carriers that use the time division multiplexing (TDMA) or GSM technology worldwide, including AT&T (formerly Cingular) and T-Mobile in the U.S. WCDMA works on WCDMA cell phones as well as laptops and portable devices with WCDMA modems [1]. Users have typically experienced downstream data rates up to 400 Kbps [1]. WCDMA has been used in the Japanese Freedom of Mobile Multimedia Access (FOMA) system and in the Universal Mobile Telecommunications System (UMTS); a third generation follow-on to the 2G GSM networks deployed worldwide [1]. Although TDMA and GSM carriers both use TDMA modulation, WCDMA stems from CDMA. Part of the 3GPP initiative, the International Telecommunication Union (ITU) refers to WCDMA as the Direct Sequence (DS) interface within the IMT-2000 global 3G standards [1]

Implementable Wireless Access for B3G Networks - III: Complexity Reducing Transceiver Structures

This article presents a comprehensive overview of some of the research conducted within Mobile VCE’s Core Wireless Access Research Programme,1 a key focus of which has naturally been on MIMO transceivers. The series of articles offers a coherent view of how the work was structured and comprises a compilation of material that has been presented in detail elsewhere (see references within the article). In this article MIMO channel measurements, analysis, and modeling, which were presented previously in the first article in this series of four, are utilized to develop compact and distributed antenna arrays. Parallel activities led to research into low-complexity MIMO single-user spacetime coding techniques, as well as SISO and MIMO multi-user CDMA-based transceivers for B3G systems. As well as feeding into the industry’s in-house research program, significant extensions of this work are now in hand, within Mobile VCE’s own core activity, aiming toward securing major improvements in delivery efficiency in future wireless systems through crosslayer operation

Adaptive Wireless Networking

This paper presents the Adaptive Wireless Networking (AWGN) project. The project aims to develop methods and technologies that can be used to design efficient adaptable and reconfigurable mobile terminals for future wireless communication systems. An overview of the activities in the project is given. Furthermore our vision on adaptivity in wireless communications and suggestions for future activities are presented

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

As semiconductor technologies continues to scale, more and more cores are being integrated on the same multicore chip. This increase in complexity poses the challenge of efficient data transfer between these cores. Several on-chip network architectures are proposed to improve the design flexibility and communication efficiency of such multicore chips. However, in a larger system consisting of several multicore chips across a board or in a System-in-Package (SiP), the performance is limited by the communication among and within these chips. Such systems, most commonly found within computing modules in typical data center nodes or server racks, are in dire need of an efficient interconnection architecture. Conventional interchip communication using wireline links involve routing the data from the internal cores to the peripheral I/O ports, travelling over the interchip channels to the destination chip, and finally getting routed from the I/O to the internal cores there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Furthermore, the intrachip and interchip communication architectures are separately designed to maximize design flexibility. Jointly designing them could, however, improve the communication efficiency significantly and yield better solutions. Previous attempts at this include an all-photonic approach that provides a unified inter/intra-chip optical network, based on recent progress in nano-photonic technologies. Works on wireless inter-chip interconnects successfully yielded better results than their wired counterparts, but their scopes were limited to establishing a single wireless connection between two chips rather than a communication architecture for a system as a whole. In this thesis, the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package is proposed. The design utilizes on-chip wireless transceivers with dimensions spanning up to tens of centimeters. It manages to seamlessly bind both intrachip and interchip communication architectures and enables direct chip-to-chip communication between the internal cores. It is shown through cycle accurate simulations that the proposed design increases the bandwidth and reduces the energy consumption when compared to the state-of-the-art wireline I/O based multichip communications

Design Trade-offs for reliable On-Chip Wireless Interconnects in NoC Platforms

The massive levels of integration following Moore\u27s Law making modern multi-core chips prevail in various domains ranging from scientific applications to bioinformatics applications for consumer electronics. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn\u27t need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. An efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. A token-passing protocol proposed to grant access of the wireless channel to competing transmitters. This limits the number of simultaneous users of the communication channel to one although multiple wireless hubs are deployed over the chip. In principle, a Frequency Division Multiple Access (FDMA) based medium access scheme would improve the utilization of the wireless resources. However, this requires design of multiple very precise, high frequency transceivers in non-overlapping frequency channels. Therefore, the scalability of this approach is limited by the state-of-the-art in transceiver design. The Code Division Multiple Access (CDMA) enables multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. The CDMA protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. The CDMA based MAC protocol outperforms the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. However, the reliability of CDMA based wireless NoC\u27s is limited, as the probability of error is eminent due to synchronization delays at the receiver. The thesis proposes the use of an advanced filter which improves the performance and also reduces the error due to synchronization delays. This thesis also proposes investigation of various channel modulation schemes on token passing wireless NoC\u27s to examine the performance and reliability of the system. The trade-off between performance and energy are established for the various conditions. The results are obtained using a modified cycle accurate simulator