120 research outputs found
Testing micropipelines
Journal ArticleMicropipelines, self-timed event-driven pipelines, are an attractive way of structuring asynchronous systems that exhibit many of the advantages of general asynchronous systems, but enough structure to make the design of significant systems practical. As with any design method, testing is critical. We present a technique for testing self-timed micropipelines for stuck-at faults and for delay faults an the bundled data paths by modifying the latch and control elements to include a built-in scan path for testing. This scan path allows the processing logic in the micropipeline, to be fully tested with only a small overhead in the latch and control circuits. The test method is very similar to scan testing in synchronous systems, but the micropipeline retains its self-timed behavior during normal operation
Implementación de Circuitos Self-Timed de 2 y 4 Fases en FPGAs
Versión electrónica de la ponencia presentada en Jornadas de Computación Reconfigurable y Aplicaciones, celebrado en Madrid en 2003Aunque los dispositivos programables tipo FPGAs están diseñados para la
implementación eficiente de circuitos síncronos, en la actualidad constituyen la única
opción disponible para prototipado rápido de circuitos self-timed. En este artículo se
presentan algunas ideas para el diseño de estos circuitos en FPGAs, para dos principales
protocolo: 2 y 4 fases. Como caso de estudio, se ha elegido la multiplicación binaria.
Se ilustra el funcionamiento de estos circuitos y se realiza una comparación entre
las dos opciones de sincronización. También se resumen los principales resultados en
área, velocidad, retardo de pistas y fanout. Como marco tecnológico se utiliza una
FPGA Xilinx Virtex II
Practical advances in asynchronous design
Journal ArticleRecent practical advances in asynchronous circuit and system design have resulted in renewed interest by circuit designers. Asynchronous systems are being viewed as in increasingly viable alternative to globally synchronous system organization. This tutorial will present the current state of the art in asynchronous circuit and system design in three different areas. The first section details asynchronous control systems. The second describes a variety of approaches to asynchronous datapaths. The third section is on asynchronous and self-timed circuits applied to the design of general purpose processors
Automatic rapid prototyping of semi-custom VLSI circuits using actel FPGAs
Journal ArticleAbstract : We describe a technique for translating semi-custom VLSI circuits automatically into field programmable gate arrays (FPGAs) for rapid prototyping to develop a system. Using an array multiplier as an example of this translation, the VLSI circuits are designed using a cell-matrix based environment. The multiplier is implemented in CMOS in both synchronous and asynchronous pipelined versions, and translated into Actel FPGAs. All test chips were found to be fully functional, and the translation efficiency in terms of chip speed and area is shown
Automatic rapid prototyping of semi-custom VLSI circuits using FPGAs
Journal ArticleWe describe a technique for translating semi-custom VLSI circuits automatically, integrating two design environments, into field programmable gate arrays (FPGAs) for rapid and inexpensive prototyping. The VLSI circuits are designed using a cell-matrix based environment that produces chips with density comparable to full custom VLSI design. These circuits are translated automatically into FPGAs for testing and system development. A four-bit pipelined array multiplier is used as an example of this translation. The multiplier is implemented in CMOS in both synchronous and asynchronous pipelined versions, and translated into Actel FPGAs both automatically, and by hand for comparison. The six test chips were all found to be fully functional, and the translation efficiency in terms of chip speed and area is shown. This result demonstrates the potential of this approach to system development
A partial scan methodology for testing self-timed circuits
technical reportThis paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage. A new method is proposed to test the sequential network in this partial scan environment. Experimental data is presented to show that high fault coverage is possible using this method with only a subset of storage elements being made scannable
The NSR processor prototype
technical reportThe NSR Non Synchronous RISC processor is a general purpose processor structured as a collection of self timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines?? These units correspond to standard synchronous pipeline stages such as Instruction Fetch Instruction Decode Execute Memory Interface and Register File but each operates concurrently as a separate self timed process?? In addition to being internally self timed the units are decoupled through self timed FIFO queues between each of the units which allows a high degree of overlap in instruction execu tion?? Branches jumps and memory accesses are also decoupled through the use of additional FIFO queues which can hide the execution latency of these instructions?? The prototype im plementation of the NSR has been constructed using Actel FPGAs Field Programmable Gate Arrays ?
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