High-speed modulation of resonant CMOS photonic modulators in deep-submicron bulk-CMOS

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 71-72).Processor manufacturers have turned to parallelism to continue to improve processor performance, and the bandwidth demands of these systems have risen. Silicon photonics can lower the energy-per-bit of core-to-core and core-to-memory interconnects to help alleviate bandwidth bottlenecks. In this thesis, methods of controlling the amount of charge entering the PiN-diode structure of a photonic ring modulator are investigated to achieve high energy-efficiency in a constrained monolithic process. A digital modulator driver circuit is designed, simulated, fabricated and partially tested. This circuit uses a push-pull topology with pre emphasis to reduce the energy per bit and to prevent the ring's optical passband from shifting to the next optical channel. A flexible driver test circuit for in-situ device characterization has been developed with a device-to-circuit modeling framework. There are many tradeoffs that must be analyzed from the system, circuit, and device levels.by Benjamin Moss.S.M

Investigating thermal dependence on monolithically-integrated photonic interconnects

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 59-61).Monolithically-integrated optical link is a disruptive technology which has the promising potential to remove memory bandwidth bottleneck in the deep multicore regime. Although with the advantages of high bandwidth-density and energy-efficiency, it comes with design challenges from device, architecture and system perspectives. High thermal sensitivity of the essential optical ring resonator imposes constraints on the applicability of optical links in the electro-optical systems. To investigate the thermal dynamics as well as to develop advanced ring thermal-tuning mechanisms, real-time thermal monitoring at design stage is required. In this work we propose a thermal simulation platform which integrates system modeling aspects including the high-level architectural performance model, the physical device evaluation model, and the thermal analysis model. By introducing the compact thermal model with linear transient thermal analysis solver, system thermal dynamics can be monitored at high efficiency. We demonstrate the temperature profile of a multi-core microprocessor system running real workloads. The evaluation results show the system thermal dependence on the manufacturing process, circuit thermal crosstalk and integrated ring heater efficiency.by Yu-Hsin Chen.S.M

Design space exploration of photonic interconnects

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 109-113).As processors scale deep into the multi-core and many-core regimes, bandwidth and energy-efficiency of the on-die interconnect network have become paramount design issues. Recognizing potential limits of electrical interconnects, emerging nanophotonic integration has been recently proposed as a potential technology option for both on-chip and chip-to-chip applications. As optical links avoid the capacitive, resistive and signal integrity limits imposed upon electrical interconnects, the introduction of integrated photonics allows for efficient realization of physical connectivity that are costly to accomplish electrically. While many recent works have since cited the potential benefits of optics, inherent design tradeoffs of photonic datapath and backend components remain relatively unknown at the system-level. This thesis develops insights regarding the behavior of electrical and hybrid optoelectrical networks and systems. We present power and area models that capture the behavior of electrical interface circuits and their interactions with optical devices. To animate these models in the context of a full system, we contribute DSENT, a novel physical modeling framework capable of estimating the costs of generalized digital electronics, mixed-signal interface circuitry, and optical links. With DSENT, we enable fast power and area evaluation of entire networks to connect the dynamics of an underlying photonics interconnect to that of an otherwise electrical system. Using our methodolody, we perform a technology-driven design space exploration of intra-chip networks and highlight the importance of thermal tuning and parasitic receiver capacitances in network power consumption. We show that the performance gains enabled by photonics-inspired architectures can enable savings in total system energy even if the network is more costly. Finally, we propose a photonically interconnected DRAM system as a solution to the core-to-DRAM bandwidth bottleneck. By attacking energy consumption at the DRAM channel, chip, and bank level with integrated photoncis, we cut the power consumption of the DRAM system by 10x while remaining area neutral when compared to a projected electrical baseline.by Chen Sun.S.M

On-Chip Optical Interconnection Networks for Multi/Manycore Architectures

The rapid development of multi/manycore technologies offers the opportunity for highly parallel architectures implemented on a single chip. While the first, low-parallelism multicore products have been based on simple interconnection structures (single bus, very simple crossbar), the emerging highly parallel architectures will require complex, limited-degree interconnection networks. This thesis studies this trend according to the general theory of interconnection structures for parallel machines, and investigates some solutions in terms of performance, cost, fault-tolerance, and run-time support to shared-memory and/or message passing programming mechanisms