Netlist Decomposition and Candidate Generation for Analog IC Routing

Netlist decomposition and candidate generation is a non-conventional approach in the routing stage of the place and route (PnR) flow. While there has been significant research and advancement in the digital domain for automation with respect to this as well as other techniques, very little work has been done in the analog domain due to its complex constraints and specific requirements. With this proposed method, the most common requirements of Analog circuits are taken into consideration to provide candidate routes for netlists of analog Integrated Chips (IC). Netlist decomposition is an important stage of breaking down multi-pin nets into two-pin nets by adding additional nodes for each net. The proposed method takes into account blockages and constraints such as symmetry and bends to develop a new algorithm using Steiner trees and Hanan grids to generate optimal Steiner points. This method also breaks down multi-pin nets to 3-pin nets which reduces the wirelength and computations significantly. The decomposed net segments are run through Dijkstra algorithm to generate multiple candidates and an Integer Linear programming (ILP) solver is used to pick the best candidates that follow all the constraints and design rules. The experimental results show that overall wirelength is reduced by 5.16% while using 3-pin net decomposition when compared to 2-pin net decomposition. There is also a reduction in the number of metal layers used and the number of Steiner points generated. The method shows lesser computations when compared to other decomposition techniques as it avoids multiple reroutes to obtain Design Rule Check (DRC) clean routes

Netlist Decomposition and Candidate Generation for Analog IC Routing

Netlist decomposition and candidate generation is a non-conventional approach in the routing stage of the place and route (PnR) flow. While there has been significant research and advancement in the digital domain for automation with respect to this as well as other techniques, very little work has been done in the analog domain due to its complex constraints and specific requirements. With this proposed method, the most common requirements of Analog circuits are taken into consideration to provide candidate routes for netlists of analog Integrated Chips (IC). Netlist decomposition is an important stage of breaking down multi-pin nets into two-pin nets by adding additional nodes for each net. The proposed method takes into account blockages and constraints such as symmetry and bends to develop a new algorithm using Steiner trees and Hanan grids to generate optimal Steiner points. This method also breaks down multi-pin nets to 3-pin nets which reduces the wirelength and computations significantly. The decomposed net segments are run through Dijkstra algorithm to generate multiple candidates and an Integer Linear programming (ILP) solver is used to pick the best candidates that follow all the constraints and design rules. The experimental results show that overall wirelength is reduced by 5.16% while using 3-pin net decomposition when compared to 2-pin net decomposition. There is also a reduction in the number of metal layers used and the number of Steiner points generated. The method shows lesser computations when compared to other decomposition techniques as it avoids multiple reroutes to obtain Design Rule Check (DRC) clean routes

Algorithmic techniques for nanometer VLSI design and manufacturing closure

As Very Large Scale Integration (VLSI) technology moves to the nanoscale regime, design and manufacturing closure becomes very difficult to achieve due to increasing chip and power density. Imperfections due to process, voltage and temperature variations aggravate the problem. Uncertainty in electrical characteristic of individual device and wire may cause significant performance deviations or even functional failures. These impose tremendous challenges to the continuation of Moore's law as well as the growth of semiconductor industry. Efforts are needed in both deterministic design stage and variation-aware design stage. This research proposes various innovative algorithms to address both stages for obtaining a design with high frequency, low power and high robustness. For deterministic optimizations, new buffer insertion and gate sizing techniques are proposed. For variation-aware optimizations, new lithography-driven and post-silicon tuning-driven design techniques are proposed. For buffer insertion, a new slew buffering formulation is presented and is proved to be NP-hard. Despite this, a highly efficient algorithm which runs > 90x faster than the best alternatives is proposed. The algorithm is also extended to handle continuous buffer locations and blockages. For gate sizing, a new algorithm is proposed to handle discrete gate library in contrast to unrealistic continuous gate library assumed by most existing algorithms. Our approach is a continuous solution guided dynamic programming approach, which integrates the high solution quality of dynamic programming with the short runtime of rounding continuous solution. For lithography-driven optimization, the problem of cell placement considering manufacturability is studied. Three algorithms are proposed to handle cell flipping and relocation. They are based on dynamic programming and graph theoretic approaches, and can provide different tradeoff between variation reduction and wire- length increase. For post-silicon tuning-driven optimization, the problem of unified adaptivity optimization on logical and clock signal tuning is studied, which enables us to significantly save resources. The new algorithm is based on a novel linear programming formulation which is solved by an advanced robust linear programming technique. The continuous solution is then discretized using binary search accelerated dynamic programming, batch based optimization, and Latin Hypercube sampling based fast simulation

Covid-19 and its impacts on consumer decision-making process

The term "virus" derives from the Latin word for "venom" and refers to a microscopic infectious agent. On the other hand, "corona" is named by its shape to look like a crown ring – the scientists who coined the word coronavirus in 1968 reasoned that the virus they were studying under a microscope resembled a solar corona (Steinmetz, 2020). COVID-19 was introduced when it was first detected in late 2019 and used letters from CO-Rona-VI-rus D-isease (Bhargava, 2020). Corona infections were initially seen as cold in 1965 (Kahn & McIntosh, 2005), which is almost six decades ago. Corona was formerly thought to be a basic, non-fatal virus to human beings until 2002. Before the world witnessed a Severe Acute Respiratory Syndrome Coronavirus (SARS-CoV) outbreak in November 2002, it was assumed that this virus mainly infected animals. However, this was proven incorrect. Ten years after that, a new pathogenic coronavirus known as the Middle East Respiratory Syndrome Coronavirus (MERS-CoV) spread throughout the Middle East and caused a pandemic in several countries (Shereen et a., 2020)

Dynamic Conditional Imitation Learning for Autonomous Driving

Conditional imitation learning (CIL) trains deep neural networks, in an end-to-end manner, to mimic human driving. This approach has demonstrated suitable vehicle control when following roads, avoiding obstacles, or taking specific turns at intersections to reach a destination. Unfortunately, performance dramatically decreases when deployed to unseen environments and is inconsistent against varying weather conditions. Most importantly, the current CIL fails to avoid static road blockages. In this work, we propose a solution to those deficiencies. First, we fuse the laser scanner with the regular camera streams, at the features level, to overcome the generalization and consistency challenges. Second, we introduce a new efficient Occupancy Grid Mapping (OGM) method along with new algorithms for road blockages avoidance and global route planning. Consequently, our proposed method dynamically detects partial and full road blockages, and guides the controlled vehicle to another route to reach the destination. Following the original CIL work, we demonstrated the effectiveness of our proposal on CARLA simulator urban driving benchmark. Our experiments showed that our model improved consistency against weather conditions by four times and autonomous driving success rate generalization by 52%. Furthermore, our global route planner improved the driving success rate by 37%. Our proposed road blockages avoidance algorithm improved the driving success rate by 27%. Finally, the average kilometers traveled before a collision with a static object increased by 1.5 times. The main source code can be reached at https://heshameraqi.github.io/dynamic_cil_autonomous_driving.Comment: 14 pages, 11 figures, 7 table