Intersystem soft handover for converged DVB-H and UMTS networks

Digital video broadcasting for handhelds (DVB-H) is the standard for broadcasting Internet Protocol (IP) data services to mobile portable devices. To provide interactive services for DVB-H, the Universal Mobile Telecommunications System (UMTS) can be used as a terrestrial interaction channel for the unidirectional DVB-H network. The converged DVB-H and UMTS network can be used to address the congestion problems due to the limited multimedia channel accesses of the UMTS network. In the converged network, intersystem soft handover between DVB-H and UMTS is needed for an optimum radio resource allocation, which reduces network operation cost while providing the required quality of service. This paper deals with the intersystem soft handover between DVB-H and UMTS in such a converged network. The converged network structure is presented. A novel soft handover scheme is proposed and evaluated. After considering the network operation cost, the performance tradeoff between the network quality of service and the network operation cost for the intersystem soft handover in the converged network is modeled using a stochastic tree and analyzed using a numerical simulation. The results show that the proposed algorithm is feasible and has the potential to be used for implementation in the real environment

A Multilevel Approach to Topology-Aware Collective Operations in Computational Grids

The efficient implementation of collective communiction operations has received much attention. Initial efforts produced "optimal" trees based on network communication models that assumed equal point-to-point latencies between any two processes. This assumption is violated in most practical settings, however, particularly in heterogeneous systems such as clusters of SMPs and wide-area "computational Grids," with the result that collective operations perform suboptimally. In response, more recent work has focused on creating topology-aware trees for collective operations that minimize communication across slower channels (e.g., a wide-area network). While these efforts have significant communication benefits, they all limit their view of the network to only two layers. We present a strategy based upon a multilayer view of the network. By creating multilevel topology-aware trees we take advantage of communication cost differences at every level in the network. We used this strategy to implement topology-aware versions of several MPI collective operations in MPICH-G2, the Globus Toolkit[tm]-enabled version of the popular MPICH implementation of the MPI standard. Using information about topology provided by MPICH-G2, we construct these multilevel topology-aware trees automatically during execution. We present results demonstrating the advantages of our multilevel approach by comparing it to the default (topology-unaware) implementation provided by MPICH and a topology-aware two-layer implementation.Comment: 16 pages, 8 figure

A QoS monitoring system in a heterogeneous multi-domain DVB-H platform

The MobileTV, IPTV, and DVB standards (DVB-H/T) have been defined to offer mobile users interactive multimedia services with quality of service (QoS) consistency analogous to TV services. However, the market has yet to provide effective and economical solutions for the real-time delivery of such services to the corresponding transmitters over multi-domain IP networks. The monitoring system proposed in this paper enables the QoS in the IP networks involved in the delivery of real-time multimedia content to the transmitters to be ascertained. The system utilizes the QoS parameters defined in MPEG-2 Transport Streams to detect problems occurring in the heterogeneous multi-domain IP networks. The ability to detect problems having an adverse effect on QoS allows appropriate control actions to be determined to recover the QoS across the composite IP network. The design and implementation of the proposed QoS-Monitoring system (QoS-MS) is presented, followed by analysis of experimental results that demonstrate the feasibility of the system

Scalable video transcoding for mobile communications

Mobile multimedia contents have been introduced in the market and their demand is growing every day due to the increasing number of mobile devices and the possibility to watch them at any moment in any place. These multimedia contents are delivered over different networks that are visualized in mobile terminals with heterogeneous characteristics. To ensure a continuous high quality it is desirable that this multimedia content can be adapted on-the-fly to the transmission constraints and the characteristics of the mobile devices. In general, video contents are compressed to save storage capacity and to reduce the bandwidth required for its transmission. Therefore, if these compressed video streams were compressed using scalable video coding schemes, they would be able to adapt to those heterogeneous networks and a wide range of terminals. Since the majority of the multimedia contents are compressed using H.264/AVC, they cannot benefit from that scalability. This paper proposes a technique to convert an H.264/AVC bitstream without scalability to a scalable bitstream with temporal scalability as part of a scalable video transcoder for mobile communications. The results show that when our technique is applied, the complexity is reduced by 98 % while maintaining coding efficiency

A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)

Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multi-core neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.Comment: 17 pages, 14 figure