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Threat Analysis, Countermeaures and Design Strategies for Secure Computation in Nanometer CMOS Regime
Advancements in CMOS technologies have led to an era of Internet Of Things (IOT), where the devices have the ability to communicate with each other apart from their computational power. As more and more sensitive data is processed by embedded devices, the trend towards lightweight and efficient cryptographic primitives has gained significant momentum. Achieving a perfect security in silicon is extremely difficult, as the traditional cryptographic implementations are vulnerable to various active and passive attacks. There is also a threat in the form of hardware Trojans inserted into the supply chain by the untrusted third-party manufacturers for economic incentives. Apart from the threats in various forms, some of the embedded security applications such as random number generators (RNGs) suffer from the impacts of process variations and noise in nanometer CMOS. Despite their disadvantages, the random and unique nature of process variations can be exploited for generating unique identifiers and can be of tremendous use in embedded security.
In this dissertation, we explore techniques for precise fault-injection in cryptographic hardware based on voltage/temperature manipulation and hardware Trojan insertion. We demonstrate the effectiveness of these techniques by mounting fault attacks on state-of-the-art ciphers. Physically Unclonable Functions (PUFs) are novel cryptographic primitives for extracting secret keys from complex manufacturing variations in integrated circuits (ICs). We explore the vulnerabilities of some of the popular strong PUF architectures to modeling attacks using Machine Learning (ML) algorithms. The attacks use silicon data from a test chip manufactured in IBM 32nm silicon-on-insulator (SOI) technology. Attack results demonstrate that the majority of strong PUF architectures can be predicted to very high accuracies using limited training data. We also explore the techniques to exploit unreliable data from strong PUF architectures and effectively use them to improve the prediction accuracies of modeling attacks. Motivated by the vulnerabilities of existing PUF architectures, we present a novel modeling attack resistant PUF architecture based on non-linear computing elements. Post-silicon validation results are used to demonstrate the effectiveness of the non-linear PUF architecture against modeling and fault-injection attacks. Apart from the techniques to improve the security of PUF circuits, we also present novel solutions to improve the performance of PUF circuits from the perspectives of IC fabrication and system/protocol design. Finally, we present a statistical benchmark suite to evaluate PUFs in conceptualization phase and also to enable fine-grained security assessments for varying PUF parameters. Data compressibility analyses for validating the statistical benchmark suite are also presented
The graphic-photographic computer : aspects of interpolation
Thesis. 1978. M.S.--Massachusetts Institute of Technology. Dept. of Architecture.MICROFICHE COPY AVAILABLE IN ARCHIVES AND ROTCH.Bibliography: leaves 56-57.by Andrew Lippman.M.S
Design And Implementation Of A Digital Controller With Dsp For Half-br
DC-DC power converters play an important role in powering telecom and computing systems. With the speed improvement and cost reduction of digital control, digital controller is becoming a trend for DC-DC converters in addition to existed digital monitoring and management technology. In this thesis, digital control is investigated for DC-DC converters applications. To deeply understand the whole control systems, DC-DC converter models are investigated based on averaged state-space modeling. Considering half-bridge isolated DC-DC converter with a current doublers rectifier has advantages over other topologies especially in the application of low-voltage and high-current DC-DC converters, the thesis take it as an example for digital control modeling and implementation. In Chapter 2, unified steady-state DC models and small-signal models are developed for both symmetric and asymmetric controlled half-bridge DC-DC converters. Based on the models, digital controller design is implemented. In Chapter 3, digital modeling platforms are established based on Matlab, Digital PID design and corresponding simulation results are provided. Also some critical issues and practical requirements are discussed. In Chapter 4, a DSP-based digital controller is implemented with the TI\u27s DSP chip TMS320F2812. Related implementation methods and technologies are discussed. Finally the experimental results of a DSP-based close-loop of HB converter are provided and analyzed in Chapter 5, and thesis conclusions are given in Chapter 6
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