Design techniques for low-voltage and low-power analog-to-digital converters

With the ever-increasing demand for portable devices used in applications such as wireless communication, mobile computing, consumer electronics, etc., the scaling of the CMOS process to deep submicron dimensions becomes more important to achieve low-cost, low-power and high-performance digital systems. However, this downscaling also requires similar shrinking of the supply voltage to insure device reliability. Even though the largest amount of signal processing is done in the digital domain, the on-chip analog-to-digital interface circuitry (analog-to-digital and digital-to-analog converters) is an important functional block in the system. These converters are also required to operate with low-voltage supply. In this thesis, design techniques for low-voltage and low-power analog-to-digital converters are proposed. The specific research contributions of this work include (1) introduction of a new low-voltage switching technique for switched- capacitor circuit design, (2) development of low-voltage and low-distortion delta- sigma modulator, (3) development of low-voltage switched-capacitor multiplying digital-to-analog converter (MDAC), (4) a new architecture for the low-power Nyquist rate pipelined ADC design. These design techniques enable the implementation of low-voltage and low-power CMOS analog-to-digital converters. To demonstrate the proposed design techniques, a 0.6 V, 82 dB, 2-2 cascaded audio delta-sigma ADC, a 0.9 V, 10-bit, 20MS/s CMOS pipelined ADC and a 2.4 V, 12-bit, 10MS/s CMOS pipelined ADC were implemented in standard CMOS processes.Keywords: ADC, delta-sigma, low-voltage, low-power, switched-R

Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies

Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaSwitches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals

Low cost high-side gate drive power supply for switched reluctance machines

Author name used in this publication: K. W. E. ChengAuthor name used in this publication: Ho S. L.Version of RecordPublishe

Pipelined analog-to-digital conversion using current-mode reference shifting

Dissertação para obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresPipeline Analog-to-digital converters (ADCs) are the most popular architecture for high-speed medium-to-high resolution applications. A fundamental, but often unreferenced building block of pipeline ADCs are the reference voltage circuits. They are required to maintain a stable reference with low output impedance to drive large internal switched capacitor loads quickly. Achieving this usually leads to a scheme that consumes a large portion of the overall power and area. A review of the literature shows that the required stable reference can be achieved with either on-chip buffering or with large off-chip decoupling capacitors. On-chip buffering is ideal for system integration but requires a high speed buffer with high power dissipation. The use of a reference with off-chip decoupling results in significant power savings but increases the pads of chip, the count of external components and the overall system cost. Moreover the amount of ringing on the internal reference voltage caused by the series inductance of the package makes this solution not viable for high speed ADCs. To address this challenge, a pipeline ADC employing a multiplying digital-to-analog converter (MDAC) with current-mode reference shifting is presented. Consequently, no reference voltages and, therefore, no voltage buffers are necessary. The bias currents are generated on-chip by a reference current generator that dissipates low power. The proposed ADC is designed in a 65 nm CMOS technology and operates at sampling rates ranging from 10 to 80 MS/s. At 40 MS/s the ADC dissipates 10.8 mW from a 1.2 V power supply and achieves an SNDR of 57.2 dB and a THD of -68 dB, corresponding to an ENOB of 9.2 bit. The corresponding figure of merit is 460 fJ/step

Systematic Design Methodology for Successive – Approximation ADCs

Successive – Approximation ADCs are widely used in ultra – low – power applications. This paper describes a systematic design procedure for designing Successive – Approximation ADCs for biomedical sensor nodes. The proposed scheme is adopted in the design of a 12 bit 1 kS/s ADC. Implemented in 65 nm CMOS, the ADC consumes 354 nW at a sampling rate of 1 kS/s operating with 1.2 supply voltage. The achieved ENOB is 11.6, corresponding to a FoM of 114 fJ/conversion – step

Low voltage techniques for pipelined analog-to-digital converters

To realize pipelined ADCs in deep-submicron processes, low voltage techniques must be developed to work around problems created by limited supply voltages such as the floating switch dead zone, reduced SNR, and reduced OpAmp performance. This thesis analyzes standard and low voltage design issues for pipelined ADCs and proposes a fully-differential implementation of the OpAmp Reset Switching Technique (ORST) as a suitable low voltage design solution. The technique uses a true fully differential MDAC structure with a switching common-mode feedback to achieve increased linearity and noise performance over the previously published ORST. A pipelined ADC test chip is designed to implement the fully differential ORST technique as a proof of concept. The design also includes a simple, low power input sampling network that also allows an increased input signal range and saves power by removing the dedicated, front-end S/H. Prototype performance demonstrates the fully differential ORST and shows sampling speeds of up to 60 MS/s, 51.4 dB SNR, 58.8 dB SFDR, and 49.7 dB SNDR for an 8-bit ENOB in a 0.18 μm CMOS process with a 1 V supply. Little change in distortion is observed up to 90 MHz input frequency, demonstrating operation without a S/H

Design techniques for low-voltage analog-to-digital converter

Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low-voltage conditions. There are several well-known techniques to bypass the problem. These approaches include: (1) The clock boosting schemes (e.g. 2VDD clock signal) which cannot be used in submicron low-voltage CMOS processes as gate oxide can only tolerate the technology's maximum voltage (VDD). (2) The use of scaled/lower threshold transistors, which are not always scalable to very low voltage supplies as it could suffer from an unacceptable amount of leakage current (e.g. the switch may not be fully turned off). (3) The use of bootstrapped clocking, which has added loading and possible reliability issues. (4) The switched-opamp (SO) technique which is fully compatible with low-voltage submicron CMOS processes but the operating speed limited due to slow transients from the opamp being switched off and on. In this thesis, the Opamp-Reset Switching Technique (ORST) topology is proposed for low-voltage operation. Instead of opamps being turned on and off as in the switched-opamp technique, the sourcing amplifier is placed in the unity-gain reset configuration to provide reset level at the output. In this way, high-speed operation is possible. The technique is applied to two ADCs as examples of low-voltage design. The first design is a 10-bit 25MSPS pipelined ADC using pseudo-differential structure. It is fabricated in a 0.35-μm CMOS process. It operates at 1.4V and consumes 21mW of total power. The second design is a two-stage algorithmic ADC with highly linear input sampling circuit. In addition to the low-voltage design techniques used in the pipelined ADC, radix-based digital calibration technique for multi-stage ADC is also proposed. The ADC uses a 0.18-μm CMOS technology. It operates at 0.9V supply with total power consumption of 9mW. Experimental results show that the proposed calibration technique reduces spurious free dynamic range from 47dB to 75dB and improves signal-to-noise and distortion ratio from 40dB to 55dB after calibration

Energy Efficient Pipeline ADCs Using Ring Amplifiers

Pipeline ADCs require accurate amplification. Traditionally, an operational transconductance amplifier (OTA) configured as a switched-capacitor (SC) amplifier performs such amplification. However, traditional OTAs limit the power efficiency of ADCs since they require high quiescent current for slewing and bandwidth. In addition, it is difficult to design low-voltage OTAs in modern, scaled CMOS. The ring amplifier is an energy efficient and high output swing alternative to an OTA for SC circuits which is basically a three-stage inverter amplifier stabilized in a feedback configuration. However, the conventional ring amplifier requires external biases, which makes the ring amplifier less practical when we consider process, supply voltage, and temperature (PVT) variation. In this dissertation, three types of innovative ring amplifiers are presented and verified with state-of-the-art energy efficient pipeline ADCs. These new ring amplifiers overcome the limitations of the conventional ring amplifier and further improve energy efficiency. The first topic of this dissertation is a self-biased ring amplifier that makes the ring amplifier more practical and power efficient, while maintaining the benefits of efficient slew-based charging and an almost rail-to-rail output swing. In addition, the ring amplifiers are also used as comparators in the 1.5b sub-ADCs by utilizing the unique characteristics of the ring amplifier. This removes the need for dedicated comparators in sub-ADCs, thus further reducing the power consumption of the ADC. The prototype 10.5b 100 MS/s comparator-less pipeline ADC with the self-biased ring amplifiers has measured SNDR, SNR and SFDR of 56.6 dB (9.11b), 57.5 dB and 64.7 dB, respectively, and consumes 2.46 mW, which results in Walden Figure-of-Merit (FoM) of 46.1 fJ/ conversion∙step. The second topic is a fully-differential ring amplifier, which solves the problems of single-ended ring amplifiers while maintaining the benefits of the single-ended ring amplifiers. This differential ring-amplifier is applied in a 13b 50 MS/s SAR-assisted pipeline ADC. Furthermore, an improved capacitive DAC switching method for the first stage SAR reduces the DAC linearity errors and switching energy. The prototype ADC achieves measured SNDR, SNR and SFDR of 70.9 dB (11.5b), 71.3 dB and 84.6 dB, respectively, and consumes 1 mW. This measured performance is equivalent to Walden and Schreier FoMs of 6.9 fJ/conversion∙step and 174.9 dB, respectively. Finally, a four-stage fully-differential ring amplifier improves the small-signal gain to over 90 dB without compromising speed. In addition, a new auto-zero noise filtering method reduces noise without consuming additional power. This is more area efficient than the conventional auto-zero noise folding reduction technique. A systematic mismatch free SAR CDAC layout method is also presented. The prototype 15b 100 MS/s calibration-free SAR-assisted pipeline ADC using the four-stage ring amplifier achieves 73.2 dB SNDR (11.9b) and 90.4 dB SFDR with a 1.1 V supply. It consumes 2.3 mW resulting in Schreier FoM of 176.6 dB.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138759/1/yonglim_1.pd