248 research outputs found

    How to speedup fault-tolerant clock generation in VLSI systems-on-chip via pipelining

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    Fault-tolerant clocking schemes become inevitable when it comes to highly-reliable chip designs. Because of the additional hardware overhead, existing solutions are considerably slower than their non-reliable counterparts. In this paper, we demonstrate that pipelining is a viable approach to speed up the distributed fault-tolerant DARTS clock generation approach introduced in (FĂĽgger, Schmid, Fuchs, Kempf, EDCC'06), where a distributed Byzantine fault-tolerant tick generation algorithm has been used to replace the traditional quartz oscillator and highly balanced clock tree in VLSI Systems-on-Chip (SoCs). We provide a pipelined version of the original DARTS algorithm, termed pDARTS, together with a novel modeling and analysis framework for hardware-implemented asynchronous fault-tolerant distributed algorithms, which is employed for rigorously analyzing its correctness & performance. Our results, which have also been confirmed by the experimental evaluation of an FPGA prototype implementation, reveal that pipelining indeed allows to entirely remove the adverse effect of large interconnect delays on the achievable clock frequency, and demonstrate again that methods and results from distributed algorithms research can successfully be applied in the VLSI context

    From FPGA to ASIC: A RISC-V processor experience

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    This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ASIC

    On-Chain Timestamps Are Accurate

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    When Satoshi Nakamoto introduced Bitcoin, a central tenet was that the blockchain functions as a timestamping server. In the Ethereum era, smart contracts widely assume on-chain timestamps are mostly accurate. In this paper, we prove this is indeed the case, namely that recorded timestamps do not wildly deviate from real-world time, a property we call timeliness. Assuming a global clock, we prove that all popular mechanisms for constructing blockchains (proof-of-work, longest chain proof-of-stake, and quorum-based proof-of-stake) are timely under honest majority, but a synchronous network is a necessary condition. Next we show that all timely blockchains can be suitably modified, in a black-box fashion, such that all honest parties output exactly the same ledgers at the same round, achieving a property we call supersafety, which may be of independent interest. Conversely, we also show that supersafety implies (perfect) timeliness, completing the circle

    User access control system based on ESP32 technology

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    Mestrado de dupla diplomação com a UTFPR - Universidade Tecnológica Federal do ParanáAccess Control Systems are systems that are capable of controlling user access with permission-based databases. The majority of commercial Access Control Systems nowadays, even the expansive ones, lacks many advanced features, such as the possibility to control and configure multiple sectors over Wi-Fi (including illumination), using scheduling based permissions, and without any additional servers. This project aims to develop an Access Control System costing under US$15, capable of registering and allowing (or denying) the access of users in multiple sectors, using up to 49 modules interconnected over Wi-Fi (one being the main module, and the other the secondary modules), using web-based graphical interfaces, allowing a centralized and practical way of configuring and setting databases. The modules use low-range RFID tags to identify users, and are able to control electrical locks, illumination and micro-switches of it’s corresponding sector, and also notify adjacent sectors of entries and exits. To keep the project easy to use, all the settings and databases can be accessed, filtered and edited in a graphical web interface (HTML5 and CSS) provided by an internal webserver running at the ESP32 controllers, and available to authenticated users. The result is a low cost Access Control System that is fast, reliable and easy to use product, presenting advanced features, such as multi-sector control and with wireless (Wi-Fi) communication

    Cluster based jamming and countermeasures for wireless sensor network MAC protocols

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    A wireless sensor network (WSN) is a collection of wireless nodes, usually with limited computing resources and available energy. The medium access control layer (MAC layer) directly guides the radio hardware and manages access to the radio spectrum in controlled way. A top priority for a WSN MAC protocol is to conserve energy, however tailoring the algorithm for this purpose can create or expose a number of security vulnerabilities. In particular, a regular duty cycle makes a node vulnerable to periodic jamming attacks. This vulnerability limits the use of use of a WSN in applications requiring high levels of security. We present a new WSN MAC protocol, RSMAC (Random Sleep MAC) that is designed to provide resistance to periodic jamming attacks while maintaining elements that are essential to WSN functionality. CPU, memory and especially radio usage are kept to a minimum to conserve energy while maintaining an acceptable level of network performance so that applications can be run transparently on top of the secure MAC layer. We use a coordinated yet pseudo-random duty cycle that is loosely synchronized across the entire network via a distributed algorithm. This thwarts an attacker\u27s ability to predict when nodes will be awake and likewise thwarts energy efficient intelligent jamming attacks by reducing their effectiveness and energy-efficiency to that of non-intelligent attacks. Implementing the random duty cycle requires additional energy usage, but also offers an opportunity to reduce asymmetric energy use and eliminate energy use lost to explicit neighbor discovery. We perform testing of RSMAC against non-secure protocols in a novel simulator that we designed to make prototyping new WSN algorithms efficient, informative and consistent. First we perform tests of the existing SMAC protocol to demonstrate the relevance of the novel simulation for estimating energy usage, data transmission rates, MAC timing and other relevant macro characteristics of wireless sensor networks. Second, we use the simulation to perform detailed testing of RSMAC that demonstrates its performance characteristics with different configurations and its effectiveness in confounding intelligent jammers

    Digital signal processor fundamentals and system design

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    Digital Signal Processors (DSPs) have been used in accelerator systems for more than fifteen years and have largely contributed to the evolution towards digital technology of many accelerator systems, such as machine protection, diagnostics and control of beams, power supply and motors. This paper aims at familiarising the reader with DSP fundamentals, namely DSP characteristics and processing development. Several DSP examples are given, in particular on Texas Instruments DSPs, as they are used in the DSP laboratory companion of the lectures this paper is based upon. The typical system design flow is described; common difficulties, problems and choices faced by DSP developers are outlined; and hints are given on the best solution
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