Boosting Ethernet Performance by Segment-Based Routing

Ethernet is turning out to be a cost-effective solution for building Cluster networks offering compatibility, simpli-city, high bandwidth, scalability and a good performance-to-cost ratio. Nevertheless, Ethernet still makes inefficient use of network resources (links) and suffers from long fail-ure recovery time due to the lack of a suitable routing algo-rithm. In this paper we embed an efficient routing algorithm into 802.3 Ethernet technology, making it possible to use off-the-shelf equipment to build high-performance and cost-effective Ethernet clusters, with an efficient use of link band-width and with fault tolerant capabilities. The algorithm, referred to as Segment-Based Routing (SR), is a determinis-tic routing algorithm that achieves high performance with-out the need for virtual channels (not available in Ether-net). Moreover, SR is topology agnostic, meaning it can be applied to any topology, and tolerates any combination of faults derived from the original topology when combined with static reconfiguration. Through simulations we ver-ify an overall improvement in throughput by a factor of 1.2 to 10.0 when compared to the conventional Ethernet rou-ting algorithm, the Spanning Tree Protocol (STP), and other topology agnostic routing algorithms such as Up*/Down* and Tree-based Turn-prohibition, the last one being recently proposed for Ethernet.

Boosting the Performance of PC-based Software Routers with FPGA-enhanced Network Interface Cards

The research community is devoting increasing attention to software routers based on off-the-shelf hardware and open-source operating systems running on the personalcomputer (PC) architecture. Today's high-end PCs are equipped with peripheral component interconnect (PCI) shared buses enabling them to easily fit into the multi-gigabit-per-second routing segment, for a price much lower than that of commercial routers. However, commercially-available PC network interface cards (NICs) lack programmability, and require not only packets to cross the PCI bus twice, but also to be processed in software by the operating system, strongly reducing the achievable forwarding rate. It is therefore interesting to explore the performance of customizable NICs based on field-programmable gate array (FPGA) logic devices we developed and assess how well they can overcome the limitations of today's commercially-available NIC

Multistage Switching Architectures for Software Routers

Software routers based on personal computer (PC) architectures are becoming an important alternative to proprietary and expensive network devices. However, software routers suffer from many limitations of the PC architecture, including, among others, limited bus and central processing unit (CPU) bandwidth, high memory access latency, limited scalability in terms of number of network interface cards, and lack of resilience mechanisms. Multistage PC-based architectures can be an interesting alternative since they permit us to i) increase the performance of single software routers, ii) scale router size, iii) distribute packet manipulation and control functionality, iv) recover from single-component failures, and v) incrementally upgrade router performance. We propose a specific multistage architecture, exploiting PC-based routers as switching elements, to build a high-speed, largesize,scalable, and reliable software router. A small-scale prototype of the multistage router is currently up and running in our labs, and performance evaluation is under wa

Stateless Flow-Zone Switching Using Software-Defined Addressing

The trend toward cloudification of communication networks and services, with user data and applications stored and processed in data centers, pushes the limits of current Data Center Networks (DCNs), requiring improved scalability, resiliency, and performance. Here we consider a DCN forwarding approach based on software-defined addressing (SDA), which embeds semantics in the Medium Access Control (MAC) address and thereby enables new forwarding processes. This work presents Flow-Zone Switching (FZS), a loop-free location-based source-routing solution that eliminates the need for forwarding tables by embedding routing instructions and flow identifiers directly in the flow-zone software-defined address. FZS speeds the forwarding process, increasing the throughput and reducing the latency of QoS-sensitive flows while reducing the capital and operational costs of switching. This paper presents details of FZS and a performance evaluation within a complete DCN.This work was supported in part by the H2020 Europe/Taiwan Joint Action 5G-DIVE under Grant 859881, in part by the Spanish State Research Agency through the TRUE5G Project under Grant PID2019-108713RB-C52/AEI/10.13039/501100011033, and in part by the Comunidad de Madrid through the Project TAPIR-CM under Grant S2018/TCS-4496

Virtualization of network I/O on modern operating systems

Network I/O of modern operating systems is incomplete. In this networkage, users and their applications are still unable to control theirown traffic, even on their local host. Network I/O is a sharedresource of a host machine, and traditionally, to address problemswith a shared resource, system research has virtualized the resource.Therefore, it is reasonable to ask if the virtualization can providesolutions to problems in network I/O of modern operating systems, inthe same way as the other components of computer systems, such asmemory and CPU. With the aim of establishing the virtualization ofnetwork I/O as a design principle of operating systems, thisdissertation first presents a virtualization model, hierarchicalvirtualization of network interface. Systematic evaluation illustratesthat the virtualization model possesses desirable properties forvirtualization of network I/O, namely flexible control granularity,resource protection, partitioning of resource consumption, properaccess control and generality as a control model. The implementedprototype exhibits practical performance with expected functionality,and allowed flexible and dynamic network control by users andapplications, unlike existing systems designed solely for systemadministrators. However, because the implementation was hardcoded inkernel source code, the prototype was not perfect in its functionalcoverage and flexibility. Accordingly, this dissertation investigatedhow to decouple OS kernels and packet processing code throughvirtualization, and studied three degrees of code virtualization,namely, limited virtualization, partial virtualization, and completevirtualization. In this process, a novel programming model waspresented, based on embedded Java technology, and the prototypeimplementation exhibited the following characteristics, which aredesirable for network code virtualization. First, users program inJava to carry out safe and simple programming for packetprocessing. Second, anyone, even untrusted applications, can performinjection of packet processing code in the kernel, due to isolation ofcode execution. Third, the prototype implementation empirically provedthat such a virtualization does not jeopardize system performance.These cases illustrate advantages of virtualization, and suggest thatthe hierarchical virtualization of network interfaces can be aneffective solution to problems in network I/O of modern operatingsystems, both in the control model and in implementation

A Pragmatic View of MANET Performance Evaluation and Design of a Prototype MAC Level Routing Algorithm

Our goal in this research is to investigate and determine how to best support a challenging mobile wireless network based in a military operational environment. Since routing protocols used in mobile ad hoc networks (MANET) must adapt to frequent or continual changes of topology, while simultaneously limiting the impact of tracking these changes on wireless resources, we focused our initial research on improving the efficiency of route discovery. We proposed and designed a new MAC layer routing protocol that pursues reduced routing overhead, greater interaction of network protocol layers and passive neighbor/path discovery. This algorithm, called Virtual MAC Tag Switching (VMTS), evolved as we implemented a prototype in the ns-2 network simulator and conducted simulation analysis of existing protocols: DSDV, DSR and AODV. Upon analyzing the performance of existing routing protocols using pragmatic metrics not applied in any MANET literature it was found that current MANET models produce unsatisfactory performance. Subsequent analysis of transport layer protocol behaviors pinpointed the causes that undermine the performance of the existing protocols and would have thwarted VMTS as well

An SDN-based Overlay Networking Solution for Transparent Multi-homed Vehicular Communications

This dissertation consists in the design and development of an Overlay Network for vehicular applications using the SDN paradigm, capable of supporting seamless handover and load balancing between multiple Vehicle-to-Infrastructure (V2I) networks, and also seamless handover of users' terminals between different vehicle zones, such as train carriages. The main contributions of this work are threefold: 1) the overlay SDN-based network architecture designed for vehicular applications such as trains, contemplating the support for multiple V2I operators and multiple gateways per vehicle (e.g., one per carriage); 2) the SDN orchestration component that implements the handover (performed by a User Terminal) from one carriage to another, without Internet connection interruption; and 3) the SDN orchestration component that implements the load-balancing of traffic over multiple V2I links that connect each carriage to the Internet, optimizing the utilization of available network resources and resulting QoS. All the features related to these contributions were implemented in a centralized SDN controller, which has a holistic view of the overlay network, which orchestrates the network hardware on-board of the vehicles. A Proof-of-Concept of the overlay network and the developed components was implemented using Virtual Machines emulating: the network elements of two carriages; the user terminals; a centralized orchestrator; an Internet gateway; and multiple V2I connections representing different operators. Different functional and performance tests were executed, targeting each component, which allowed to successfully validate each contribution