A Zero Bias Pixel Sensor and its Zero-Bias Column Buffer-Direct-Injection Circuit

Two pixel sensors, namely active pixel sensor (APS) and pseudo-active pixel sensor (PAPS), are reviewed to show that APS suffers from dark current while PAPS suffers from leakage current. Then a new pixel sensor called  zero bias pixel sensor (ZBPS) in which only two MOS switches in addition to the photodiode are used, one for connecting the pixel’s photodiode to a column bus and the other for bypassing it. A zero-bias column buffer-direct-injection (ZCBDI) circuit, which is similar to a regulated cascode amplifier, is used to control the voltage at column bus at zero. All ZBPS pixels are guaranteed to work at zero voltage at all times to eliminate the dark current as well as leakage current. A case of a 10 µm x 10 µm ZBPS pixel designed with standard 0.18 µm CMOS process is studied through simulation. This pixel generates a photocurrent within a range from 1 pA to 100 nA. To handle a large variation of photocurrent while maintaining zero column voltage, the ZCBDI is designed using differential cascode, common source, and buffer stages and then compensated for 50 degree phase margin. Transient simulation shows that the pixel steady state response time is around 1.406 ms, leading to at most 5.5 frames per second for an image of 128 x 128 ZBPS pixels. The fill factor of ZBPS for this case is around 59%

MOSFET Modulated Dual Conversion Gain CMOS Image Sensors

In recent years, vision systems based on CMOS image sensors have acquired significant ground over those based on charge-coupled devices (CCD). The main advantages of CMOS image sensors are their high level of integration, random accessibility, and low-voltage, low-power operation. Previously proposed high dynamic range enhancement schemes focused mainly on extending the sensor dynamic range at the high illumination end. Sensor dynamic range extension at the low illumination end has not been addressed. Since most applications require low-noise, high-sensitivity, characteristics for imaging of the dark region as well as dynamic range expansion to the bright region, the availability of a low-noise, high-sensitivity pixel device is particularly important. In this dissertation, a dual-conversion-gain (DCG) pixel architecture was proposed; this architecture increases the signal to noise ratio (SNR) and the dynamic range of CMOS image sensors at both the low and high illumination ends. The dual conversion gain pixel improves the dynamic range by changing the conversion gain based on the illumination level without increasing artifacts or increasing the imaging readout noise floor. A MOSFET is used to modulate the capacitance of the charge sensing node. Under high light illumination conditions, a low conversion gain is used to achieve higher full well capacity and wider dynamic range. Under low light conditions, a high conversion gain is enabled to lower the readout noise and achieve excellent low light performance. A sensor prototype using the new pixel architecture with 5.6μm pixel pitch was designed and fabricated using Micron Technology’s 130nm 3-metal and 2-poly silicon process. The periphery circuitries were designed to readout the pixel and support the pixel characterization needs. The pixel design, readout timing, and operation voltage were optimized. A detail sensor characterization was performed; a 127μV/e was achieved for the high conversion gain mode and 30.8μV/e for the low conversion gain mode. Characterization results confirm that a 42ke linear full well was achieved for the low conversion gain mode and 10.5ke for the high conversion gain mode. An average 2.1e readout noise was measured for the high conversion gain mode and 8.6e for the low conversion gain mode. The total sensor dynamic range was extended to 86dB by combining the two modes of operation with a 46.2dB maximum SNR. Several images were taken by the prototype sensor under different illumination levels. The simple processed color images show the clear advantage of the high conversion gain mode for the low light imaging

DESIGN OF A BURST MODE ULTRA HIGH-SPEED LOW-NOISE CMOS IMAGE SENSOR

Ultra-high-speed (UHS) image sensors are of interest for studying fast scientific phenomena and may also be useful in medicine. Several published studies have recently achieved frame rates of up to millions of frames per second (Mfps) using advanced processes and/or customized processes. This thesis presents a burst-mode (108 frames) UHS low-noise CMOS image sensor (CIS) based on charge-sweep transfer gates in an unmodified, standard 180 nm front-side-illuminated CIS process. By optimizing the photodiode geometry, the 52.8 μm pitch pixels with 20x20 μm^2 of active area, achieve a charge-transfer time of less than 10 ns. A proof-of-concept CIS was designed and fabricated. Through characterization, it is shown that the designed CIS has the potential to achieve 20 Mfps with an input-referred noise of 5.1 e− rms

High Resolution Active Pixel Sensor X-Ray Detectors for Digital Breast Tomosynthesis

Current large area x-ray detectors for digital breast tomosynthesis (DBT) are based on the amorphous silicon (a-Si:H) passive pixel sensor (PPS) technology. However, PPS detectors suffer from a limited resolution and high electronic noise. In this dissertation, we propose high resolution large area active pixel sensor (APS) x-ray detectors based on the complementary metal-oxide-semiconductor (CMOS) and amorphous In-Sn-Zn-O (a-ITZO) thin-film transistor (TFT) technologies to improve the imager resolution and noise properties. We evaluated the two-dimensional (2D) x-ray imaging performance as measured by the modulation transfer function (MTF), noise power spectrum (NPS) and detective quantum efficiency (DQE) for both 75 µm (Dexela 2923 MAM) and 50 µm pixel pitch (DynAMITe) CMOS APS x-ray detectors. Excellent imaging performance (DQE in the range of 0.7 – 0.3) has been achieved over the entire spatial frequency range (0 – 6.7 mm-1) at low air kerma below 10 µGy using the 75 µm pixel pitch Dexela 2923 MAM detector. The 50 μm pixel pitch DyAMITe detector has further extended the spatial resolution of the detector to 10 mm-1 with a low electronic noise of 150 e-. Also, a 2D cascaded system analysis model has been developed to describe the signal and noise transfer for the CMOS APS x-ray imaging systems. We also implemented three-dimensional (3D) cascaded system analysis to simulated the 3D MTF, NPS and DQE characteristics using DBT radiation conditions and acquisition geometries. The 3D cascaded system analysis for the DynAMITe detector was integrated with an object task function, a medical imaging display model, and the human eye contrast sensitivity function to calculate the detectability index and area under the ROC curve (AUC). It has been demonstrated that the display pixel pitch and zoom factor should be optimized to improve the AUC for detecting high contrast objects such as microcalcifications. Also, detector electronic noise of smaller than 300 e- and a high display maximum luminance (>1000 cd/cm2) are desirable to distinguish microcalcifications of 150 µm or smaller in size. For low contrast object detection, a medical imaging display with a minimum of 12 bits gray levels is needed to realize accurate luminance levels. A wide projection angle range (≥ ±30°) combined with the image gray level magnification could improve the detectability for low contrast objects especially when the anatomical background noise is high. CMOS APS x-ray detectors demonstrate both a high pixel resolution and low electronic noise, but are challenging to be fabricated in a large detector size greater than the wafer scale. Alternatively, current-mode APS (C-APS) based on a-ITZO TFTs was proposed for DBT due to the high gain, low noise, and capability to realize a large detector area. Specifically, we fabricated a-ITZO TFTs and achieved a high field-effect mobility of >30 cm2/Vs. We have also evaluated the electrical performance of a 50 µm pixel pitch a-ITZO TFT C-APS combined with an a-Si:H p+-i-n+ photodiode using SPICE simulation. The proposed C-APS circuit demonstrates a high charge gain of 885 with data line loadings considered. A pixel circuit layout and fabrication process have also been suggested. Finally, noise analysis has been applied to the a-ITZO TFT C-APS. A low electronic noise of around 239 e- has been established. The research presented in this thesis indicates that APS x-ray detectors based on both CMOS and a-ITZO TFT technologies are promising for next generation DBT systems.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/136983/1/zhaocm_1.pd

Development of ASIC for SiPM sensor readout

L'abstract è presente nell'allegato / the abstract is in the attachmen

Interfacing of neuromorphic vision, auditory and olfactory sensors with digital neuromorphic circuits

The conventional Von Neumann architecture imposes strict constraints on the development of intelligent adaptive systems. The requirements of substantial computing power to process and analyse complex data make such an approach impractical to be used in implementing smart systems. Neuromorphic engineering has produced promising results in applications such as electronic sensing, networking architectures and complex data processing. This interdisciplinary field takes inspiration from neurobiological architecture and emulates these characteristics using analogue Very Large Scale Integration (VLSI). The unconventional approach of exploiting the non-linear current characteristics of transistors has aided in the development of low-power adaptive systems that can be implemented in intelligent systems. The neuromorphic approach is widely applied in electronic sensing, particularly in vision, auditory, tactile and olfactory sensors. While conventional sensors generate a huge amount of redundant output data, neuromorphic sensors implement the biological concept of spike-based output to generate sparse output data that corresponds to a certain sensing event. The operation principle applied in these sensors supports reduced power consumption with operating efficiency comparable to conventional sensors. Although neuromorphic sensors such as Dynamic Vision Sensor (DVS), Dynamic and Active pixel Vision Sensor (DAVIS) and AEREAR2 are steadily expanding their scope of application in real-world systems, the lack of spike-based data processing algorithms and complex interfacing methods restricts its applications in low-cost standalone autonomous systems. This research addresses the issue of interfacing between neuromorphic sensors and digital neuromorphic circuits. Current interfacing methods of these sensors are dependent on computers for output data processing. This approach restricts the portability of these sensors, limits their application in a standalone system and increases the overall cost of such systems. The proposed methodology simplifies the interfacing of these sensors with digital neuromorphic processors by utilizing AER communication protocols and neuromorphic hardware developed under the Convolution AER Vision Architecture for Real-time (CAVIAR) project. The proposed interface is simulated using a JAVA model that emulates a typical spikebased output of a neuromorphic sensor, in this case an olfactory sensor, and functions that process this data based on supervised learning. The successful implementation of this simulation suggests that the methodology is a practical solution and can be implemented in hardware. The JAVA simulation is compared to a similar model developed in Nengo, a standard large-scale neural simulation tool. The successful completion of this research contributes towards expanding the scope of application of neuromorphic sensors in standalone intelligent systems. The easy interfacing method proposed in this thesis promotes the portability of these sensors by eliminating the dependency on computers for output data processing. The inclusion of neuromorphic Field Programmable Gate Array (FPGA) board allows reconfiguration and deployment of learning algorithms to implement adaptable systems. These low-power systems can be widely applied in biosecurity and environmental monitoring. With this thesis, we suggest directions for future research in neuromorphic standalone systems based on neuromorphic olfaction

A CMOS 90nm Digital Pixel Sensor Intended for a Visual Cortical Stimulator

RÉSUMÉ La capture d’images et le traitement d’images et de signaux font partie des domaines les plus en vogue de nos jours. Un autre domaine qui retient l’attention des chercheurs à travers le monde est celui qui regroupe les applications biomédicales - en particulier celles qui font le pont entre l’électronique et la biologie. L’équipe Polystim œuvre sur différents projets à la pointe de la technologie qui touchent à ces domaines, dont le projet Cortivision: un stimulateur visuel cortical. Le système englobe la capture et le traitement d’images ainsi que la stimulation du cortex pour donner une certaine perception d’images aux patients souffrant de cécité. Le but de ce travail est de concevoir le module de capture d’images de ce système. Les modes d’opération du capteur d’images doivent être configurables par l’usager. Il doit se distinguer par une gamme dynamique élevée, une consommation de puissance réduite, une haute vitesse d’acquisition, une surface réduite, la portabilité, la possibilité d’avoir du traitement d’images sur puce, et la facilité de l’intégrer dans un système sur puce avec le reste des modules de Cortivision. Un DPS (Digital Pixel Sensor) CMOS a été conçu et fabriqué avec la nouvelle technologie CMOS 90nm. Chaque pixel comprend une photodiode, un circuit de conversion de photocourant, un convertisseur analogique à numérique et une mémoire numérique de 8 bits, dans une surface de 9 µm x 9 µm avec un facteur de remplissage de 26% et 57 transistors. Le capteur offre plusieurs modes d’opération: • Un mode d’intégration linéaire. • Un mode logarithmique avec une gamme dynamique étendue qui permet d’accéder aux pixels indépendamment du temps mais avec une diminution de linéarité et un bruit plus prononcé. • Un mode différentiel qui soustrait deux images successives à même la puce pour obtenir une image binaire. Ce mode permet d’accélérer le traitement d’images et fonctionne à une vitesse plus élevée. Il peut être utilisé simultanément avec le mode linéaire ou avec le mode logarithmique. • Un mode d’expositions multiples qui est une option du mode linéaire pour augmenter la gamme dynamique, mais qui aurait l’effet de réduire la vitesse d’acquisition.----------ABSTRACT The image sensing and image processing fields make up some of the hottest topics in today’s industrial and research communities. Another field that is getting a lot of attention is biomedical applications - especially the combination of electronics to biology. The Polystim team is working on some state-of-the-art projects encompassing all that. One of these is the Cortivision project that consists of a visual cortical stimulator. The system comprises image sensing, image processing, and brain cortex stimulation to help blind patients acquire a sense of visual perception. The goal of this work is to cover the image sensing portion of the system. This requires the design and implementation of an image sensor which is user configurable to operate in several modes, has a high dynamic range, low power consumption, high frame rate capability, reduced surface area, is portable, allows some on-chip image processing, and can easily be integrated in a system-on-chip with the rest of the Cortivision modules. A CMOS Digital Pixel Sensor was designed and fabricated using the novel CMOS 90nm technology. Each pixel consists of a Photodiode, a photo-current conversion circuit, an Analog-to-Digital Converter and a digital 8-bit memory. It has a pixel pitch of 9µm with a Fill-Factor of 26% and 57 transistors. The sensor offers several modes of operation: • A linear integration mode. • A logarithmic mode that extends the dynamic range and allows time-independent pixel access at the cost of a forsaken linearity and an increase in noise. • A differential (or better termed difference) mode that allows subtracting two consecutive frames to obtain a binary image. This mode helps speed up the image processing and allows a very high frame rate. It can be used in conjunction with either the linear or the logarithmic modes of operation. • A multiple exposure mode that can be used in combination with the linear mode to increase the dynamic range at the expense of a decrease in frame rate

Organic Photodiodes and Their Optoelectronic Applications

Recently, organic photodiodes (OPDs) have been acknowledged as a next-generation device for photovoltaic and image sensor applications due to their advantages of large area process, light weight, mechanical flexibility, and excellent photoresponse. This dissertation targets for the development and understanding of high performance organic photodiodes for their medical and industrial applications for the next-generation. As the first research focus, A dielectric / metal / dielectric (DMD) transparent electrode is proposed for the top-illumination OPDs. The fabricated DMD transparent electrode showed the maximum optical transmittance of 85.7 % with sheet resistance of 6.2 ohm/sq. In the second part of the thesis, a development of novel transfer process which enables the dark current suppression for the inverted OPD devices will be discussed. Through the effort, we demonstrated OPD with high D* of 4.82 x 10^12 Jones at reverse bias of 1.5 V with dark current density (Jdark) of 7.7 nA/cm2 and external quantum efficiency (EQE) of 60 %. Additionally in the third part, we investigate a high performance low-bandgap polymer OPD with broadband spectrum. By utilizing the novel transfer process to introduce charge blocking layers, significant suppression of the dark current is achieved while high EQE of the device is preserved. A low Jdark of 5 nA/cm2 at reverse bias of 0.5 V was achieved resulting in the highest D* of 1.5 x 10^13 Jones. To investigate the benefit for the various OPD applications, we developed a novel 3D printing technique to fabricate OPD on hemispherical concave substrate. The techniques allowed the direct patterning of the OPD devices on hemispherical substrates without excessive strain or deformation. Lastly, a simulation of the OPD stacked a-ITZO TFT active pixel sensor (APS) pixel with external transimpedance amplifier (TIA) readout circuit was performed.PHDElectrical & Computer Eng PhDUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137168/1/hyunskim_1.pd

Speckle pattern interferometry : vibration measurement based on a novel CMOS camera

A digital speckle pattern interferometer based on a novel custom complementary metaloxide- semiconductor (CMOS) array detector is described. The temporal evolution of the dynamic deformation of a test object is measured using inter-frame phase stepping. The flexibility of the CMOS detector is used to identify regions of interest with full-field time averaged measurements and then to interrogate those regions with time-resolved measurements sampled at up to 7 kHz. The maximum surface velocity that can be measured and the number of measurement points are limited by the frame rate and the data transfer rate of the detector. The custom sensor used in this work is a modulated light camera (MLC), whose pixel design is still based on the standard four transistor active pixel sensor (APS), but each pixel has four large independently shuttered capacitors that drastically boost the well capacity from that of the diode alone. Each capacitor represents a channel which has its own shutter switch and can either be operated independently or in tandem with others. The particular APS of this camera enables a novel approach in how the data are acquired and then processed. In this Thesis we demonstrate how, at a given frame rate and at a given number of measurement points, the data transfer rate of our system is increased if compared to the data transfer rate of a system using a standard approach. Moreover, under some assumptions, the gain in system bandwidth doesn’t entail any reduction in the maximum surface velocity that can be reliably measured with inter-frame phase stepping