181 research outputs found

    Classification and properties of fast linearly independent logic transformations

    Full text link

    A study of arithmetic circuits and the effect of utilising Reed-Muller techniques

    Get PDF
    Reed-Muller algebraic techniques, as an alternative means in logic design, became more attractive recently, because of their compact representations of logic functions and yielding of easily testable circuits. It is claimed by some researchers that Reed-Muller algebraic techniques are particularly suitable for arithmetic circuits. In fact, no practical application in this field can be found in the open literature.This project investigates existing Reed-Muller algebraic techniques and explores their application in arithmetic circuits. The work described in this thesis is concerned with practical applications in arithmetic circuits, especially for minimizing logic circuits at the transistor level. These results are compared with those obtained using the conventional Boolean algebraic techniques. This work is also related to wider fields, from logic level design to layout level design in CMOS circuits, the current leading technology in VLSI. The emphasis is put on circuit level (transistor level) design. The results show that, although Boolean logic is believed to be a more general tool in logic design, it is not the best tool in all situations. Reed-Muller logic can generate good results which can't be easily obtained by using Boolean logic.F or testing purposes, a gate fault model is often used in the conventional implementation of Reed-Muller logic, which leads to Reed-Muller logic being restricted to using a small gate set. This usually leads to generating more complex circuits. When a cell fault model, which is more suitable for regular and iterative circuits, such as arithmetic circuits, is used instead of the gate fault model in Reed-Muller logic, a wider gate set can be employed to realize Reed-Muller functions. As a result, many circuits designed using Reed-Muller logic can be comparable to that designed using Boolean logic. This conclusion is demonstrated by testing many randomly generated functions.The main aim of this project is to develop arithmetic circuits for practical application. A number of practical arithmetic circuits are reported. The first one is a carry chain adder. Utilising the CMOS circuit characteristics, a simple and high speed carry chain is constructed to perform the carry operation. The proposed carry chain adder can be reconstructed to form a fast carry skip adder, and it is also found to be a good application for residue number adders. An algorithm for an on-line adder and its implementation are also developed. Another circuit is a parallel multiplier based on 5:3 counter. The simulations show that the proposed circuits are better than many previous designs, in terms of the number of transistors and speed. In addition, a 4:2 compressor for a carry free adder is investigated. It is shown that the two main schemes to construct the 4:2 compressor have a unified structure. A variant of the Baugh and Wooley algorithm is also studied and generalized in this work

    Synthesis and Optimization of Reversible Circuits - A Survey

    Full text link
    Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

    Spectral Methods for Boolean and Multiple-Valued Input Logic Functions

    Get PDF
    Spectral techniques in digital logic design have been known for more than thirty years. They have been used for Boolean function classification, disjoint decomposition, parallel and serial linear decomposition, spectral translation synthesis (extraction of linear pre- and post-filters), multiplexer synthesis, prime implicant extraction by spectral summation, threshold logic synthesis, estimation of logic complexity, testing, and state assignment. This dissertation resolves many important issues concerning the efficient application of spectral methods used in the computer-aided design of digital circuits. The main obstacles in these applications were, up to now, memory requirements for computer systems and lack of the possibility of calculating spectra directly from Boolean equations. By using the algorithms presented here these obstacles have been overcome. Moreover, the methods presented in this dissertation can be regarded as representatives of a whole family of methods and the approach presented can be easily adapted to other orthogonal transforms used in digital logic design. Algorithms are shown for Adding, Arithmetic, and Reed-Muller transforms. However, the main focus of this dissertation is on the efficient computer calculation of Rademacher-Walsh spectra of Boolean functions, since this particular ordering of Walsh transforms is most frequently used in digital logic design. A theory has been developed to calculate the Rademacher-Walsh transform from a cube array specification of incompletely specified Boolean functions. The importance of representing Boolean functions as arrays of disjoint ON- and DC- cubes has been pointed out, and an efficient new algorithm to generate disjoint cubes from non-disjoint ones has been designed. The transform algorithm makes use of the properties of an array of disjoint cubes and allows the determination of the spectral coefficients in an independent way. By such an approach each spectral coefficient can be calculated separately or all the coefficients can be calculated in parallel. These advantages are absent in the existing methods. The possibility of calculating only some coefficients is very important since there are many spectral methods in digital logic design for which the values of only a few selected coefficients are needed. Most of the current methods used in the spectral domain deal only with completely specified Boolean functions. On the other hand, all of the algorithms introduced here are valid, not only for completely specified Boolean functions, but for functions with don\u27t cares. Don\u27t care minterms are simply represented in the form of disjoint cubes. The links between spectral and classical methods used for designing digital circuits are described. The real meaning of spectral coefficients from Walsh and other orthogonal spectra in classical logic terms is shown. The relations presented here can be used for the calculation of different transforms. The methods are based on direct manipulations on Karnaugh maps. The conversion start with Karnaugh maps and generate the spectral coefficients. The spectral representation of multiple-valued input binary functions is proposed here for the first time. Such a representation is composed of a vector of Walsh transforms each vector is defined for one pair of the input variables of the function. The new representation has the advantage of being real-valued, thus having an easy interpretation. Since two types of codings of values of binary functions are used, two different spectra are introduced. The meaning of each spectral coefficient in classical logic terms is discussed. The mathematical relationships between the number of true, false, and don\u27t care minterms and spectral coefficients are stated. These relationships can be used to calculate the spectral coefficients directly from the graphical representations of binary functions. Similarly to the spectral methods in classical logic design, the new spectral representation of binary functions can find applications in many problems of analysis, synthesis, and testing of circuits described by such functions. A new algorithm is shown that converts the disjoint cube representation of Boolean functions into fixed-polarity Generalized Reed-Muller Expansions (GRME). Since the known fast algorithm that generates the GRME, based on the factorization of the Reed-Muller transform matrix, always starts from the truth table (minterms) of a Boolean function, then the described method has advantages due to a smaller required computer memory. Moreover, for Boolean functions, described by only a few disjoint cubes, the method is much more efficient than the fast algorithm. By investigating a family of elementary second order matrices, new transforms of real vectors are introduced. When used for Boolean function transformations, these transforms are one-to-one mappings in a binary or ternary vector space. The concept of different polarities of the Arithmetic and Adding transforms has been introduced. New operations on matrices: horizontal, vertical, and vertical-horizontal joints (concatenations) are introduced. All previously known transforms, and those introduced in this dissertation can be characterized by two features: ordering and polarity . When a transform exists for all possible polarities then it is said to be generalized . For all of the transforms discussed, procedures are given for generalizing and defining for different orderings. The meaning of each spectral coefficient for a given transform is also presented in terms of standard logic gates. There exist six commonly used orderings of Walsh transforms: Hadamard, Rademacher, Kaczmarz, Paley, Cal-Sal, and X. By investigating the ways in which these known orderings are generated the author noticed that the same operations can be used to create some new orderings. The generation of two new Walsh transforms in Gray code orderings, from the straight binary code is shown. A recursive algorithm for the Gray code ordered Walsh transform is based on the new operator introduced in this presentation under the name of the bi-symmetrical pseudo Kronecker product . The recursive algorithm is the basis for the flow diagram of a constant geometry fast Walsh transform in Gray code ordering. The algorithm is fast (N 10g2N additions/subtractions), computer efficient, and is implemente

    Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form

    Get PDF
    In this paper, we present biconditional binary deci- sion diagrams (BBDDs), a novel canonical representation form for Boolean functions. BBDDs are binary decision diagrams where the branching condition, and its associated logic expansion, is biconditional on two variables. Empowered by reduction and ordering rules, BBDDs are remarkably compact and unique for a Boolean function. The interest of such representation form in modern electronic design automation (EDA) is twofold. On the one hand, BBDDs improve the efficiency of traditional EDA tasks based on decision diagrams, especially for arithmetic intensive designs. On the other hand, BBDDs represent the natural and native design abstraction for emerging technologies where the circuit primitive is a comparator, rather than a simple switch. We provide, in this paper, a solid ground for BBDDs by studying their underlying theory and manipulation properties. Thanks to an efficient BBDD software package implementation, we validate 1) speed-up in traditional decision diagrams applications with up to 4.4 gain with respect to other DDs, and 2) improved synthesis of circuits in emerging technologies, with about 32% shorter critical path than state-of-art synthesis techniques

    Algorithms in computer-aided design of VLSI circuits.

    Get PDF
    With the increased complexity of Very Large Scale Integrated (VLSI) circuits,Computer Aided Design (CAD) plays an even more important role. Top-downdesign methodology and layout of VLSI are reviewed. Moreover, previouslypublished algorithms in CAD of VLSI design are outlined.In certain applications, Reed-Muller (RM) forms when implemented withAND/XOR or OR/XNOR logic have shown some attractive advantages overthe standard Boolean logic based on AND/OR logic. The RM forms implementedwith OR/XNOR logic, known as Dual Forms of Reed-Muller (DFRM),is the Dual form of traditional RM implemented with AND /XOR.Map folding and transformation techniques are presented for the conversionbetween standard Boolean and DFRM expansions of any polarity. Bidirectionalmulti-segment computer based conversion algorithms are also proposedfor large functions based on the concept of Boolean polarity for canonicalproduct-of-sums Boolean functions. Furthermore, another two tabular basedconversion algorithms, serial and parallel tabular techniques, are presented forthe conversion of large functions between standard Boolean and DFRM expansionsof any polarity. The algorithms were tested for examples of up to 25variables using the MCNC and IWLS'93 benchmarks.Any n-variable Boolean function can be expressed by a Fixed PolarityReed-Muller (FPRM) form. In order to have a compact Multi-level MPRM(MMPRM) expansion, a method called on-set table method is developed.The method derives MMPRM expansions directly from FPRM expansions.If searching all polarities of FPRM expansions, the MMPRM expansions withthe least number of literals can be obtained. As a result, it is possible to findthe best polarity expansion among 2n FPRM expansions instead of searching2n2n-1 MPRM expansions within reasonable time for large functions. Furthermore,it uses on-set coefficients only and hence reduces the usage of memorydramatically.Currently, XOR and XNOR gates can be implemented into Look-Up Tables(LUT) of Field Programmable Gate Arrays (FPGAs). However, FPGAplacement is categorised to be NP-complete. Efficient placement algorithmsare very important to CAD design tools. Two algorithms based on GeneticAlgorithm (GA) and GA with Simulated Annealing (SA) are presented for theplacement of symmetrical FPGA. Both of algorithms could achieve comparableresults to those obtained by Versatile Placement and Routing (VPR) toolsin terms of the number of routing channel tracks

    Logic synthesis and optimisation using Reed-Muller expansions

    Get PDF
    This thesis presents techniques and algorithms which may be employed to represent, generate and optimise particular categories of Exclusive-OR SumOf-Products (ESOP) forms. The work documented herein concentrates on two types of Reed-Muller (RM) expressions, namely, Fixed Polarity Reed-Muller (FPRM) expansions and KROnecker (KRO) expansions (a category of mixed polarity RM expansions). Initially, the theory of switching functions is comprehensively reviewed. This includes descriptions of various types of RM expansion and ESOP forms. The structure of Binary Decision Diagrams (BDDs) and Reed-Muller Universal Logic Module (RM-ULM) networks are also examined. Heuristic algorithms for deriving optimal (sub-optimal) FPRM expansions of Boolean functions are described. These algorithms are improved forms of an existing tabular technique [1]. Results are presented which illustrate the performance of these new minimisation methods when evaluated against selected existing techniques. An algorithm which may be employed to generate FPRM expansions from incompletely specified Boolean functions is also described. This technique introduces a means of determining the optimum allocation of the Boolean 'don't care' terms so as to derive equivalent minimal FPRM expansions. The tabular technique [1] is extended to allow the representation of KRO expansions. This new method may be employed to generate KRO expansions from either an initial incompletely specified Boolean function or a KRO expansion of different polarity. Additionally, it may be necessary to derive KRO expressions from Boolean Sum-Of-Products (SOP) forms where the product terms are not minterms. A technique is described which forms KRO expansions from disjoint SOP forms without first expanding the SOP expressions to minterm forms. Reed-Muller Binary Decision Diagrams (RMBDDs) are introduced as a graphical means of representing FPRM expansions. RMBDDs are analogous to the BDDs used to represent Boolean functions. Rules are detailed which allow the efficient representation of the initial FPRM expansions and an algorithm is presented which may be employed to determine an optimum (sub-optimum) variable ordering for the RMBDDs. The implementation of RMBDDs as RM-ULM networks is also examined. This thesis is concluded with a review of the algorithms and techniques developed during this research project. The value of these methods are discussed and suggestions are made as to how improved results could have been obtained. Additionally, areas for future work are proposed
    • …
    corecore