980 research outputs found

    Body diode reliability investigation of SiC power MOSFETs

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    A special feature of vertical power MOSFETs, in general, is the inbuilt body diode which could eliminate the need of having to use additional anti-parallel diodes for current freewheeling in industrial inverter applications: this, clearly, subject to their demonstration of an acceptable level of reliability. Recent improvements in Silicon Carbide (SiC) power MOSFET device manufacturing technology has resulted in their wider commercial availability with different voltage and current ratings and from various manufacturers. Hence, it is essential to perform characterisation of its intrinsic body diode. This paper presents the reliability assessment of body diodes of latest generation discrete SiC power MOSFETs within a 3-phase 2-level DC-to-AC inverter representing realistic operating conditions for power electronic applications

    Bias temperature instability and condition monitoring in SiC power MOSFETs

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    Threshold voltage shift due to bias temperature instability (BTI) is a major concern in SiC power MOSFETs. The SiC/SiO2 gate dielectric interface is typically characterized by a higher density of interface traps compared to the conventional Si/SiO2 interface. The threshold voltage shift that arises from BTI has significant implications on the reliability of SiC power MOSFETs, hence, techniques for detecting the change in electrical parameters due to gate oxide degradation are desirable. Using accelerated high temperature gate bias stress tests on SiC MOSFETs, it has been shown that the output and transfer characteristics are affected by BTI. This paper presents the impact BTI induced threshold voltage shift on the forward voltage of the SiC MOSFET body diode during third quadrant operation. Using the forward voltage of the body diode during reverse conduction of low currents, threshold voltage shift can be detected, hence, the impact of BTI can be evaluated. The implications of the body diode forward voltage shift on junction temperature measurements are also studied in the context of TSEPs. The findings in this paper are important for engineers seeking to implement condition and health monitoring techniques on SiC power devices

    A novel non-intrusive technique for BTI characterization in SiC MOSFETs

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    Threshold voltage ( VTHV_{TH} ) shift due to Bias Temperature Instability (BTI) is a well-known problem in SiC-MOSFETs that occurs due to oxide traps in the SiC/SiO2SiC/SiO_2 gate interface. The reduced band offsets and increased interface/fixed oxide traps in SiC-MOSFETs makes this a more critical problem compared to silicon. Before qualification, power devices are subjected to gate bias stress tests after which VTHV_{TH} shift is monitored. However, some recovery occurs between the end of the stress and VTHV_{TH} characterisation, thereby potentially under-estimating the extent of the problem. In applications where the SiC-MOSFET is turned OFF with a negative bias at high temperature, if VTHV_{TH} shift is severe enough there may be electrothermal failure due to current crowding since parallel devices lose synchronization during turn-ON. In this paper, a novel method that uses the forward voltage of the body diode during reverse conduction of a small sensing current is introduced as a technique for monitoring VTHV_{TH} shift and recovery due to BTI. This non-invasive method exploits the increased body effect that is peculiar SiC-MOSFETs due to the higher body diode forward voltage. With the proposed method, it is possible to non-invasively assess VTHV_{TH} shift dynamically during BTI characterization tests

    Impact of the gate oxide reliability of SiC MOSFETs on the junction temperature estimation using temperature sensitive electrical parameters

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    Bias temperature instability (BTI) is more problematic in SiC power MOSFETs due to the occurrence of higher interface state traps and fixed oxide traps compared to traditional silicon MOS interfaces where there are no carbon atoms degrading the atomically smooth Si/SiO2 interface. The use of temperature sensitive electrical parameters (TSEPs) for measuring the junction temperature and enabling health monitoring based on junction temperature identification is a promising technique for increasing the reliability of power devices, however in the light of increased BTI in SiC devices, this must be carefully assessed. This paper evaluates how BTI of SiC power MOSFETs under high temperature gate bias stresses affects the electrical parameters used as TSEPs and its impact on condition monitoring

    Reliability analysis of planar and symmetrical & asymmetrical trench discrete SiC Power MOSFETs

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    Silicon Carbide MOSFETs are shown in research to outperform Silicon counterparts on many performance metrics, including switching rates and power losses. To further improve their performance, trench and double-trench structures have recently been developed. To replace conventional planar SiC MOSFETs, besides the performance parameters which are mostly stated in datasheets, reliability studies under stress are also needed. This thesis presents a comprehensive comparison between 3rd generation trench SiC power MOSFETs, namely symmetrical double-trench and asymmetrical trench with planar SiC power MOSFETs on four aspects of: switching slew rates (dI/dt & dV/dt), crosstalk characteristics, bias temperature instability and power cycling stability.First, the dynamic performance in both 1st quadrant and 3rd quadrant has been eval- uated on the differences in stress by dI/dt & dV/dt and resultant losses. This is key in understanding many other reliability criterions, i.e. severity of crosstalk induced switchings. In the 1st quadrant, the source current and drain-source voltage switching rates at both turn-ON and turn-OFF are measured under a range of test conditions. Both the symmetrical and asymmetrical trench MOSFETs have up to 2 times faster voltage and current slew rates compared with the planar one. They also indicate only slight changes in switching rate with junction temperature. In the 3rd quadrant, the reverse recovery peak current and total reverse recovery charge are measured with respect to junction temper- ature and load current level. Both the symmetrical and asymmetrical trench MOSFETs have less than half of the reverse recovery charge of that of the planar SiC MOSFET.In the evaluation of crosstalk characteristics, peak shoot-through current and induced gate voltage at crosstalk are measured with respect to junction temperature and external gate resistance. With particularly large external gate resistances connected to intentionally induce parasitic turn-ON, the symmetrical double-trench MOSFET is shown to be more prone to crosstalk with 23 A peak shoot-through current measured while it is only 10 A for asymmetrical trench and 4 A for planar MOSFET under similar test conditions. As the temperature increase, the peak shoot-through current drops for the symmetrical double-trench, while constant for the asymmetrical trench and rising for the planar device.Threshold voltage drift is also measured to reflect the degradation happened with bias temperature instability at various junction temperatures, stressing voltages and time periods. Under low-magnitude gate stress (within the range of datasheets) in both positive and negative bias cases, there is more threshold drift observed on the two trench MOSFETs at all junction temperatures than the planar MOSFET. When the stress magnitude is raised, there is less threshold drift observed on the two trench MOSFETs.To evaluate the ruggedness in continuous switchings, the devices are placed under repetitive turn-ON events. The thermal performance under such operation are compared. The asymmetrical trench MOSFET experiences the highest case temperature rise while the least is observed for the planar MOSFET. With an external heatsink equipped to achieve more efficient cooling, the repetitive turn-ON test transforms into the conventional power cycling. In this condition, both the symmetrical and asymmetrical trench MOSFETs fail earlier than the degraded (but not failed) planar MOSFET

    Charracterisation and Analysis of High Voltage Silicon Carbide Mosfet

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    Non-intrusive methodologies for characterization of bias temperature instability in SiC power MOSFETs

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    The gate oxide reliability of SiC power MOSFETs remains a challenge, despite the improvements of the new generation power devices. The threshold voltage drift caused by Bias Temperature Instability (BTI) has been subject of different studies and methods have been proposed to evaluate the real magnitude of the threshold voltage shift. These methodologies usually focus on the characterization of the threshold voltage shift, rather than its implications to the operation or how the threshold voltage shift can be detected during the application. This paper presents two non-intrusive methodologies which can assess and determine the impact of BTI-induced. The proposed methodologies are able to capture the peak shift and subsequent recovery after stress removal

    Impact of Short-Circuit Events on the Remaining Useful Life of SiC MOSFETs and Mitigation Strategy

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    Single pulse avalanche robustness and repetitive stress ageing of SiC power MOSFETs

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    This paper presents an extensive electro-thermal characterisation of latest generation silicon carbide (SiC) Power MOSFETs under unclamped inductive switching (UIS) conditions. Tests are carried out to thoroughly understand the single pulse avalanche ruggedness limits of commercial SiC MOSFETs and assess their aging under repetitive stress conditions. Both a functional and a structural characterisation of the transistors is presented, with the aim of informing future device technology development for robust and reliable power system development
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