DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

Built-In Self Test (BIST) for Realistic Delay Defects

Testing of delay defects is necessary in deep submicron (DSM) technologies. High coverage delay tests produced by automatic test pattern generation (ATPG) can be applied during wafer and package tests, but are difficult to apply during the board test, due to limited chip access. Delay testing at the board level is increasingly important to diagnose failures caused by supply noise or temperature in the board environment. An alternative to ATPG is the built-in self test (BIST). In combination with the insertion of test points, BIST is able to achieve high coverage of stuck-at and transition faults. The quality of BIST patterns on small delay defects is an open question. In this work we analyze the application of BIST to small delay defects using resistive short and open models in order to estimate the coverage and correlate the coverage to traditional delay fault models

A Hierachical Infrastrucutre for SOC Test Management

HD2BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system

A High-level EDA Environment for the Automatic Insertion of HD-BIST Structures

This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in System-on-Chip applications. HD-BIST allows activating and controlling different BISTed blocks at different levels of hierarchy, with a minimum overhead in terms of area and test time. Besides the hardware layer, the authors present the HD-BIST application layer, where a simple modeling language, and a prototypical EDA tool demonstrate the effectiveness of the automation of the HD-BIST insertion in the test strategy definition of a complex System-on-Chip

U.S. Extended Continental Shelf Cruise to Map Gaps in Kela and Karin Ridges, Johnston Atoll, Equatorial Pacific Ocean

The objectives for cruise KM14-17 are to map the bathymetry of two gaps in two submarine ridges in the vicinity of Johnston Atoll. One ridge gap occurs along the informally named Keli Ridge (Hein et al., 2005) south of Johnston Atoll and the other ridge gap occurs north of Johnston Atoll that separates Sculpin Ridge (also informally called Karin Ridge) and Horizon Ridge, all in the central equatorial Pacific (Fig. 1). The cruise took advantage of a scheduled dead-head transit from Papeete, Tahiti to Honolulu, Hawai’i that could be extended for 5 days to include the planned mapping. The mapping is in support of the U.S. (Extended Continental Shelf (ECS) Task Force. These areas were identified by the ECS Central Pacific Integrated Regional Team as having the potential for an ECS

U.S. Law of the Sea Cruise to Complete the Mapping of Necker Ridge, Central Pacific Ocean

U.S. Law of the Sea Cruise to Complete the Mapping of Necker Ridge, Central Pacific Ocean CRUISE KM1121 July 31, to August 10, 2011 Honolulu, HI to Honolulu, H

Board-Level BIST Based on the 1149.1 Standard

The progress in the fields of miniaturisation (surface mount technology, large pin count ICs, etc.) andintegration density (due to feature size reduction, and exploited by the availability of highly sophisticatedCAD design tools) has made it possible to design very complex printed circuit boards (PCBs), whichpresent very high testability requirements. Boundary Scan design and test is now largely accepted as oneof the most promising solutions for this challenge, with an increasing number of off-the-shelf BSTcomponents becoming available, and easy-to-use software tools which automate the development of theboundary scan infrastructure for ASIC design. Board-level test, which was the main driving force behindthe development of the BST standard, is however still waiting for an integrated family of componentsable to address three main requirements: the test of non-BST clusters, analog I/O interface, and board-levelBIST capability. Proposed solutions for these problems have been published and some componentsare available, but a much larger offer for board-level designers is still required.This paper proposes a board-level BIST strategy based on three types of testability building blocks: theinterface to non-BST digital I/O nodes, the interface to analog I/O nodes, and a dedicated test processorproviding the board-level test capability. It is shown that, by following careful design rules, it is possibleto implement all the proposed building blocks in medium-complexity programmable logic devices(PLDs) widely available, therefore providing a low-cost and maximum-flexibility solution for board-levelBIST. Moreover, and since these testability blocks were implemented using a simple and powerfulhardware design language (HDL), any changes due to specific board requirements can easily be made

U.S. Law of the Sea Cruise to Map the Southern Flank of the Kingman Reef-Palmyra Atoll section of the Line Islands, Equatorial Pacific Ocean

U.S. Law of the Sea Cruise to Map the Southern Flank of the Kingman Reef-Palmyra Atoll section of the Line Islands, Equatorial Pacific Ocean CRUISE KM1009 May 17, to June 16, 2010 Pago Pago, American Samoa to Honolulu, H